SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

257

Revision 1.4 (08-19-08)

 

This register is used in the Auto-Negotiation process.

The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.

Since the Virtual PHY link partner is emulated, there is never a Parallel Detection Fault
and this bit is always 0.

Next page ability is not supported by the Virtual PHY or emulated link partner.

The page received bit is clear when read. It is first cleared on reset, but set shortly
thereafter when the Auto-Negotiation process is run.

The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no
common bits between the advertised ability and the link partner ability).

Offset:
Index (decimal):

1D8h
6

Size:

32 bits

31:16

RESERVED
(See 

)

RO

-

15:5

RO

-

4

Parallel Detection Fault
This bit indicates whether a Parallel Detection Fault has been detected. This 
bit is always 0.

RO

0b

3

Link Partner Next Page Able
This bit indicates whether the link partner has next page ability. This bit is 
always 0.

RO

0b

2

Local Device Next Page Able
This bit indicates whether the local device has next page ability. This bit is 
always 0.

RO

0b

1

Page Received
This bit indicates the reception of a new page.

RO/LH

1b

0

Link Partner Auto-Negotiation Able
This bit indicates the Auto-negotiation ability of the link partner.

RO

1b