SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

260

SMSC LAN9311/LAN9311i

 

This section details the remainder of the System CSR’s. These registers allow for monitoring and
configuration of various LAN9311/LAN9311i functions such as the Chip ID/revision, byte order testing,
power management, hardware configuration, general purpose timer, and free running counter.

This read-only register contains the ID and Revision fields for the LAN9311/LAN9311i.

Default value is dependent on device revision.

Offset:

050h

Size:

32 bits

31:16

Chip ID
This field indicates the chip ID.

RO

9311h

15:0

Chip Revision
This field indicates the design revision.

RO