SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

296

SMSC LAN9311/LAN9311i

 

The Pause and Asymmetric Pause bits are loaded into the PHY registers by the EEPROM
Loader.

The default value of this bit is determined by the Manual Flow Control Enable Strap
(manual_FC_strap_x). When the Manual Flow Control Enable Strap is 0, this bit defaults
to 1 (symmetric pause advertised). When the Manual Flow Control Enable Strap is 1, this
bit defaults to 0 (symmetric pause not advertised). Configuration strap values are latched
upon the de-assertion of a chip-level reset as described in 

. Refer to 

 for

configuration strap definitions.

The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
(autoneg_strap_x) with the logical AND of the negated speed select strap (speed_strap_x)
and (duplex_strap_x). 

 defines the default behavior of this bit. Configuration

strap values are latched upon the de-assertion of a chip-level reset as described in 

. Refer to 

 for configuration strap definitions.

The default value of this bit is determined by the logical OR of the Auto-Negotiation strap
(autoneg_strap_x) and the negated speed strap (speed_strap_x). 

 defines the

default behavior of this bit. Configuration strap values are latched upon the de-assertion
of a chip-level reset as described in 

Refer to 

 for configuration strap

definitions.

4:0

Selector Field
This field identifies the type of message being sent by Auto-Negotiation.

R/W

00001b

0

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

1

0

0

1

0

1

0

1

0

1