SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

309

Revision 1.4 (08-19-08)

 

This section details the various LAN9311/LAN9311i switch control and status registers that reside
within the switch fabric. The switch control and status registers allow configuration of each individual
switch port, the switch engine, and buffer manager. Switch fabric related interrupts and resets are also
controlled and monitored via the switch CSRs.

The switch CSRs are not memory mapped. All switch CSRs are accessed indirectly via the 

, and 

 in the system CSR memory mapped address space. All accesses to

the switch CSRs must be performed through these registers. Refer to 

for additional information.

The flow control settings of the switch ports are configured via the 

 registers: 

, and 

located in the system CSR address space.

 lists the Switch CSRs and their corresponding addresses in order. The switch fabric

registers can be categorized into the following sub-sections:

„

„

„

„

0000h

SW_DEV_ID

Switch Device ID Register, 

0001h

SW_RESET

Switch Reset Register, 

0002h-0003h

RESERVED

Reserved for Future Use

0004h

SW_IMR

Switch Global Interrupt Mask Register, 

0005h

SW_IPR

Switch Global Interrupt Pending Register, 

0006h-03FFh

RESERVED

Reserved for Future Use

0400h

MAC_VER_ID_MII

Port 0 MAC Version ID Register, 

0401h

MAC_RX_CFG_MII

Port 0 MAC Receive Configuration Register, 

0402h-040Fh

RESERVED

Reserved for Future Use

0410h

MAC_RX_UNDSZE_CNT_MII

Port 0 MAC Receive Undersize Count Register, 

0411h

MAC_RX_64_CNT_MII

Port 0 MAC Receive 64 Byte Count Register, 

0412h

MAC_RX_65_TO_127_CNT_MII

Port 0 MAC Receive 65 to 127 Byte Count Register, 

0413h

MAC_RX_128_TO_255_CNT_MII

Port 0 MAC Receive 128 to 255 Byte Count Register,