SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

322

SMSC LAN9311/LAN9311i

 

This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch
related interrupts in the 

 may be masked via this

register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will
unmask the interrupt. When an unmasked switch fabric interrupt is generated in the 

, the interrupt will trigger the SWITCH_INT bit in the 

. Refer to 

 for more information.

Register #:

0004h

Size:

32 bits

31:9

RO

-

8:7

These bits must be written as 11b

R/W

11b

6

Buffer Manager Interrupt Mask (BM)
When set, prevents the generation of switch fabric interrupts due to the 
Buffer Manager via the 

. The status bits in the SW_IPR register are not affected.

R/W

1b

5

Switch Engine Interrupt Mask (SWE)
When set, prevents the generation of switch fabric interrupts due to the 
Switch Engine via the 

The status bits in the SW_IPR register are not affected.

R/W

1b

4:3

These bits must be written as 11b

R/W

11b

2

Port 2 MAC Interrupt Mask (MAC_2)
When set, prevents the generation of switch fabric interrupts due to the Port 
2 MAC via the MAC_IPR_2 register (see 

). 

The status bits in the SW_IPR register are not affected.

R/W

1b

1

Port 1 MAC Interrupt Mask (MAC_1)
When set, prevents the generation of switch fabric interrupts due to the Port 
1 MAC via the MAC_IPR_1 register (see 

). 

The status bits in the SW_IPR register are not affected.

R/W

1b

0

Port 0 MAC Interrupt Mask (MAC_MII)
When set, prevents the generation of switch fabric interrupts due to the Port 
0 MAC via the MAC_IPR_MII register (see 

The status bits in the SW_IPR register are not affected.

R/W

1b