SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

346

SMSC LAN9311/LAN9311i

 

This read/write register configures the transmit packet parameters of the port.

Register #:

Port0: 0440h

Size:

32 bits

Port1: 0840h
Port2: 0C40h

31:8

RO

-

7

MAC Counter Test 
When set, TX and RX counters that normally clear to 0 when read, will be 
set to 7FFF_FFFCh when read with the exception of the 

and 

 counters which will be set to 

7FFF_FF80h.

R/W

0b

6:2

IFG Config
These bits control the transmit inter-frame gap.
IFG bit times = (IFG Config *4) + 12

R/W

10101b

1

TX Pad Enable
When set, packets shorter than 64 bytes are padded with zeros if needed 
and a FCS is appended. Packets that are 60 bytes or less will become 64 
bytes. Packets that are 61, 62, and 63 bytes will become 65, 66, and 67 
bytes respectively.

R/W

1b

0

TX Enable
When set, the transmit port is enabled. When cleared, the transmit port is 
disabled.

R/W

1b