SMSC LAN9311 User Manual
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08)
382
SMSC LAN9311/LAN9311i
DATASHEET
14.5.3.13
Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA)
This register is used to write the DIFFSERV table. The DIFFSERV table is not initialized upon reset
on power-up. If DIFFSERV is enabled, the full table should be initialized by the host.
on power-up. If DIFFSERV is enabled, the full table should be initialized by the host.
Register #:
1812h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31:3
RESERVED
RO
-
2:0
DIFFSERV Priority
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
These bits specify the assigned receive priority for IP packets with a ToS/CS
field that matches this index.
R/W
000b