SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

53

Revision 1.4 (08-19-08)

 

„

TX Status FIFO Overflow

„

Receive Watchdog Time-Out

„

Receiver Error

„

Transmitter Error

„

TX Data FIFO Underrun

„

TX Data FIFO Overrun

„

TX Data FIFO Available

„

TX Status FIFO Full

„

TX Status FIFO Level

„

RX Dropped Frame

„

RX Data FIFO Level

„

RX Status FIFO Full

„

RX Status FIFO Level

In order for a Host MAC interrupt event to trigger the external IRQ interrupt pin, the desired Host MAC
interrupt event must be enabled in the 

, and IRQ output must be

enabled via bit 8 (IRQ_EN) of the 

 and 

for additional information on bit definitions and Host MAC operation.

Multiple Power Management Event interrupt sources are provided by the LAN9311/LAN9311i. The top-
level PME_INT (bit 17) of the 

 provides indication that a Power

Management interrupt event occurred in the 

.

The 

 provides enabling/disabling and status of all

Power Management conditions. These include energy-detect on the Port 1/2 PHYs, and Wake-On-LAN
(wake-up frame or magic packet) detection by the Host MAC.

In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired
Power Management interrupt event must be enabled in the 

 (bits 15, 14, and/or 9), bit 17 (PME_INT_EN) of the 

must be set, and IRQ output must be enabled via bit 8 (IRQ_EN) of the 

.

For additional details on power management, refer to 

.

A General Purpose Timer (GPT) interrupt is provided in the top-level 

 and 

 (bit 19). This interrupt is issued when the 

 wraps past zero to FFFFh, and is cleared when bit

19 of the 

 is written with 1.

In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT
must be enabled via the bit 29 (TIMER_EN) in the 

, bit 19 of the 

 must be set, and IRQ output must be

enabled via bit 8 (IRQ_EN) of the 

For additional details on the General Purpose Timer, refer to