SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

SMSC LAN9311/LAN9311i

57

Revision 1.4 (08-19-08)

 

To perform a read of an individual switch fabric register, the read cycle must be initiated by performing
a single write to the 

 with

CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the desired register address, the
R_nW (bit 30) set, and the AUTO_INC and AUTO_DEC fields cleared. Valid data is available for
reading when the CSR_BUSY bit is cleared, indicating that the data can be read from the 

.

A second read method may be used which utilizes the auto increment/decrement function of the 

 for reading sequential register

addresses. When using this method, the 

 must first be written with the auto increment(AUTO_INC) or auto

decrement(AUTO_DEC) bit set, the CSR_ADDRESS field written with the desired register address,
and the R_nW bit set. The completion of a read cycle is indicated by the clearing of the CSR_BUSY
bit, at which time the data can be read from the 

. When the data is read, the address in the 

 is incremented or decremented accordingly, and another

read cycle is started automatically. The user should clear the AUTO_INC and AUTO_DEC bits before
reading the last data to avoid an unintended read cycle.

 illustrates the process required to perform a switch fabric CSR read. The minimum wait

periods as specified in 

 are required where

noted.

Idle

Write Data 

Register

Write 

Command 

Register

Read 

Command 

Register

CSR_BUSY = 0

CSR_BUSY = 1

Idle

Write Data 

Register

Write 

Command 

Register

Read 

Command 

Register

CSR_BUSY = 0

CSR_BUSY = 1

Idle

Write 

Direct 

Data 

Register 

Range

Read 

Command 

Register

CSR_BUSY = 0

CSR_BUSY = 1

min wait period

min wait period

min wait period