Siemens ERTEC200 User Manual

 

The memory protection unit enables the user to partition specific memory areas (I-cache, D-cache, or DTCM) into 
various regions and to assign different attributes to them. 
A maximum of 8 regions of variable size can be set. If regions overlap, the attributes of the higher region number apply.  
Settings for each region: 

• 

Base address of region 

• 

Size of region 

• 

Cache and “write buffer” configuration 

• 

Read/write access enable for privileged users/users 

 
Settings are made in the following registers of the ARM946E-S: 
ƒ Register 

2 

“Cache configuration register” 

ƒ Register 

3 

“Write buffer control register” 

ƒ Register 

5 

“Access permission register” 

ƒ Register 

6 

“Protection region/base size register” 

 
The base address defines the start address of the region. It must always be a multiple of the size of the region.  
Example: The region size is 4 Kbytes. The starting address is then always a multiple of 4 Kbytes. 
 
Before the MPU is enabled, at least one region must have been assigned. Otherwise, the ARM946E-S can assume a 
state that can only be cancelled by a reset. 
The MPU can be enabled by setting Bit 0 of the CP15 control register. 
If the MPU is disabled, the I-cache- and D-cache cannot be accessed, even if they are enabled. 
 
For more information about the MPU refer to Document /1/ Section 4. 
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document. 

The ARM946E-S uses an AHB bus master interface to the multilayer AHB bus for opcode fetches and data transfers. 
The interface operates at a fixed frequency of 50 MHz. The data bus and address bus each have a width of 32 bits. 
 
For more information about the bus interface and write buffer, and about the different transfer types, refer to Document 
/1/ Section 6. 
 

An ETM9 module is connected at the ARM946E-S. This module permits debugging support for data and instruction 
traces in the ERTEC 200. The module contains all signals required by the processor for the data and instruction traces. 
The ETM9 module is operated by means of the JTAG interface. The trace information is provided outwards to the trace 
port via a FIFO memory. A detailed description can be found in Section 11 
 

 
The interrupt controller supports the FIQ and IRQ interrupt levels of the ARM946 processor. An interrupt controller with 8 
interrupt inputs is implemented for FIQ. Six interrupt inputs (FIQ0-5) are occupied by the ERTEC 200, and 2 interrupt 
inputs (FIQ6-7) can be programmed optionally as IRQ sources. The high-priority FIQ interrupts are used for watchdog 
and address area monitoring and for debugging. An interrupt controller for 16 interrupt inputs is implemented for IRQ. Of 
the 16 IRQ inputs, two IRQ sources can be selected for as Fast-Interrupt_Requests  (FIQ6-7) for processing. The 
assignment is made by specifying the IRQ number of the relevant interrupt input in the FIQ1REG / FIQ2REG register. 
The interrupt inputs selected as FIQ must be disabled for the IRQ logic. All other interrupt inputs can continue to be 
processed as IRQs.  
The interrupt controller is operated at a clock frequency of 50 MHz. Interrupt-request signals generated with a higher 
frequency must be lengthened accordingly for error-free detection. 

 

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