Intel 80C186XL User Manual
DIRECT MEMORY ACCESS UNIT
10-16
Figure 10-11. DMA Control Register (Continued)
Register Name:
DMA Control Register
Register Mnemonic:
DxCON
Register Function:
Controls DMA channel parameters.
Bit
Mnemonic
Bit Name
Reset
State
Function
TC
Terminal
Count
Count
X
Set TC to terminate transfers on Terminal Count. This bit
is ignored for unsynchronized transfers (that is, the DMA
channel behaves as if TC is set, regardless of its
condition).
is ignored for unsynchronized transfers (that is, the DMA
channel behaves as if TC is set, regardless of its
condition).
INT
Interrupt
X
Set INT to generate an interrupt request on Terminal
Count. The TC bit must be set to generate an interrupt.
Count. The TC bit must be set to generate an interrupt.
SYN1:0
Synchron-
ization Type
ization Type
XX
Selects channel synchronization:
SYN1 SYN0
Synchronization Type
0
0
Unsynchronized
0
1
Source-synchronized
1
0
Destination-synchronized
1
1
Reserved (do
not
use)
P
Relative
Priority
Priority
X
Set P to select high priority for the channel; clear P to
select low priority for the channel.
select low priority for the channel.
IDRQ
Internal
DMA
Request
Select
DMA
Request
Select
X
Set IDRQ to select internal DMA requests and ignore
the external DRQ pin. Clear IDRQ to select the DRQ pin
as the source of DMA requests. When IDRQ is set, the
channel must be configured for source-synchronized
transfers (SYN1:0 = 01).
the external DRQ pin. Clear IDRQ to select the DRQ pin
as the source of DMA requests. When IDRQ is set, the
channel must be configured for source-synchronized
transfers (SYN1:0 = 01).
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
logic zero to ensure compatibility with future Intel products.
15
0
S
T
R
T
T
R
T
C
H
G
H
G
W
O
R
D
R
D
P
S
Y
N
Y
N
0
S
Y
N
Y
N
1
I
D
R
Q
R
Q
T
C
S
I
N
C
C
S
D
E
C
D
E
C
I
N
T
D
I
N
C
C
D
D
E
C
D
E
C
D
M
E
M
S
M
E
M
A1180-0A