Fujitsu CM71-00101-5E User Manual
78
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.7
ADDN2 (Add Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to
word data in "Ri", stores the results to "Ri" without changing flag settings.
word data in "Ri", stores the results to "Ri" without changing flag settings.
■
ADDN2 (Add Immediate Data to Destination Register)
Assembler format:
ADDN2 #i4, Ri
Operation:
Ri + extn(i4) +
→
Ri
Flag change:
N, Z, V, and C: Unchanged
Execution cycles:
1 cycle
Instruction format:
Example:
ADDN2 #–2, R3
N
Z
V
C
–
–
–
–
MSB
LSB
1
0
1
0
0
0
0
1
i4
Ri
R3
9 9 9 9
9 9 9 9
N Z V C
CCR
R3
CCR
0 0 0 0
N Z V C
0 0 0 0
9 9 9 9
9 9 9 7
Instruction bit pattern :1010 0001 1110 0011
Before execution
After execution