Fujitsu CM71-00101-5E User Manual
85
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.14
AND (And Word Data of Source Register to Destination
Register)
Register)
Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the
results to "Ri".
results to "Ri".
■
AND (And Word Data of Source Register to Destination Register)
Assembler format:
AND Rj, Ri
Operation:
Ri and Rj
→
Ri
Flag change:
N:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z:
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
1 cycle
Instruction format:
Example:
AND R2, R3
N
Z
V
C
C
C
–
–
MSB
LSB
1
0
0
0
0
0
1
0
Rj
Ri
R2
R3
1 1 1 1
0 0 0 0
1 0 1 0
1 0 1 0
N Z V C
CCR
R2
R3
CCR
0 0 0 0
N Z V C
0 0 0 0
1 0 1 0
0 0 0 0
1 1 1 1
0 0 0 0
Before execution
After execution
Instruction bit pattern : 1000 0010 0010 0011