Fujitsu CM71-00101-5E User Manual
132
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.40
DIV1 (Main Process of Division)
This instruction is used in unsigned division. It should be used in combinations such as
DIV0U and DIV1 x 32.
DIV0U and DIV1 x 32.
■
DIV1 (Main Process of Division)
Assembler format:
DIV1 Ri
Operation:
{MDH, MDL} < < = 1
if (D1 = = 1) {
if (D1 = = 1) {
MDH + Ri
→
temp
}
else {
else {
MDH – Ri
→
temp
}
if ((D0 eor D1 eor C) = = 0) {
if ((D0 eor D1 eor C) = = 0) {
temp
→
MDH
1
→
MDL [0]
}
Flag change:
N and V: Unchanged
Z: Set when the result of step division is "0", cleared otherwise. Set according to remainder of
division results, not according to quotient.
C: Set when the operation result of step division involves a carry operation, cleared otherwise.
Execution cycles:
d cycle(s)
Normally executed within one cycle. However, a 2-cycle interlock is applied if the instruction
immediately after is one of the following: MOV MDH, Ri / MOV MDL, Ri / ST Rs, @-R15.
Rs : dedicated register (TBR, RP, USP, SSP, MDH, MDL)
Instruction format:
N
Z
V
C
–
C
–
C
MSB
LSB
1
0
0
1
0
1
1
1
0
1
1
0
Ri