Fujitsu CM71-00101-5E User Manual

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CHAPTER 7  DETAILED EXECUTION INSTRUCTIONS

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Assembler format:

LSL2 #u4, Ri

Operation:

Ri << {u4 + 16} 

→

 Ri

Flag change:    

N:  Set when the MSB of the operation result is "1", cleared when the MSB is "0".

Z:  Set when the operation result is "0", cleared otherwise.

V: Unchanged

C:  Holds the bit value shifted last. 

Execution cycles:  

1 cycle

Instruction format:  

Example:

LSL2 #8, R3

N

Z

V

C

C

C

–

C

MSB

LSB

1

0

1

1

0

1

0

1

u4

Ri

R3

R3

F F 0 0 0 0 0 0

F F F F F F F F

N Z V C

CCR

CCR

N Z V C

1 0 0 1

0 0 0 0

Instruction bit pattern : 

1011 0101 1000 0011

Before execution

After execution