Fujitsu CM71-00101-5E User Manual
203
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.99
Bcc:D (Branch Relative if Condition Satisfied)
This is a branching instruction with a delay slot.
If the conditions established for each particular instruction are satisfied, branch to the
address indicated by "label9" relative to the value of the program counter (PC). When
calculating the address, double the value of "rel8" as a signed extension.
If conditions are not satisfied, no branching can occur.
Conditions for each instruction are listed in Table 7.99-1.
If the conditions established for each particular instruction are satisfied, branch to the
address indicated by "label9" relative to the value of the program counter (PC). When
calculating the address, double the value of "rel8" as a signed extension.
If conditions are not satisfied, no branching can occur.
Conditions for each instruction are listed in Table 7.99-1.
■
Bcc:D (Branch Relative if Condition Satisfied)
Assembler format:
BRA : D
label9
BV : D
label9
BNO : D
label9
BNV : D
label9
BEQ : D
label9
BLT : D
label9
BNE : D
label9
BGE : D
label9
BC : D
label9
BLE : D
label9
BNC : D
label9
BGT : D
label9
BN : D
label9
BLS : D
label9
BP : D
label9
BHI : D
label9
Operation:
if (conditions satisfied) {
PC + 2 + exts (rel8 × 2)
→
PC
}
Flag change:
N, Z, V, and C: Unchanged
Table 7.99-1 Branching Conditions
Mnemonic
cc
Conditions
Mnemonic
cc
Conditions
BRA : D
0000
B
Always satisfied
BV : D
1000
B
V = 1
BNO : D
0001
B
Always unsatisfied
BNV : D
1001
B
V = 0
BEQ : D
0010
B
Z = 1
BLT : D
1010
B
V xor N = 1
BNE : D
0011
B
Z = 0
BGE : D
1011
B
V xor N = 0
BC : D
0100
B
C = 1
BLE : D
1100
B
(V xor N) or Z = 1
BNC : D
0101
B
C = 0
BGT : D
1101
B
(V xor N) or Z = 0
BN : D
0110
B
N = 1
BLS : D
1110
B
C or Z = 1
BP : D
0111
B
N = 0
BHI : D
1111
B
C or Z = 0
N
Z
V
C
–
–
–
–