Fujitsu CM71-00101-5E User Manual
231
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.117
COPLD (Load 32-bit Data from Register to Coprocessor
Register)
Register)
Transfers the 16-bit data consisting of parameters "CC", "Rj", "CRi" to the coprocessor
indicated by channel number "u4", then on the next cycle transfers the contents of CPU
general-purpose register "Rj" to that coprocessor.
Basically, this operation transfers data to a register within the coprocessor. The 32-bit
data stored in CPU general-purpose register "Rj" is transferred to coprocessor register
"CRi". Note that the actual interpretation of the fields "CC", "Rj", "CRi" is done by the
coprocessor so that the detailed actual operation is determined by the specifications of
the coprocessor.
If the coprocessor designated by the value "u4" is not mounted, a "coprocessor not
found" trap is generated.
If the coprocessor designated by the value "u4" has generated an error in a previous
operation, a "coprocessor error" trap is generated.
indicated by channel number "u4", then on the next cycle transfers the contents of CPU
general-purpose register "Rj" to that coprocessor.
Basically, this operation transfers data to a register within the coprocessor. The 32-bit
data stored in CPU general-purpose register "Rj" is transferred to coprocessor register
"CRi". Note that the actual interpretation of the fields "CC", "Rj", "CRi" is done by the
coprocessor so that the detailed actual operation is determined by the specifications of
the coprocessor.
If the coprocessor designated by the value "u4" is not mounted, a "coprocessor not
found" trap is generated.
If the coprocessor designated by the value "u4" has generated an error in a previous
operation, a "coprocessor error" trap is generated.
■
COPLD (Load 32-bit Data from Register to Coprocessor Register)
Assembler format:
COPLD #u4, #CC, Rj, CRi
Operation:
CC, Rj, CRi
→
Coprocessor on channel u4
Rj
→
CRi
Flag change:
N, Z, V, and C: Unchanged
Execution cycles:
1 + 2a cycles
Instruction format:
N
Z
V
C
–
–
–
–
MSB
LSB
1
0
0
1
1
1
1
1
1
1
0
1
u4
(n+0)
CRi
Rj
CC
(n+2)