Fujitsu CM71-00101-5E User Manual

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CHAPTER 4  RESET AND "EIT" PROCESSING

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Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined.

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The following operating sequence takes place when an undefined instruction exception occurs.

(1) The contents of the program status (PS) are saved to the system stack.

(2) The address of the instruction that caused the undefined-instruction exception is saved to the system

stack.

(3) The value of the system stack pointer (SSP) is reduced by 8.

(4) The value "0" is written to the "S" flag in the condition code register (CCR) in the "PS".

(5) The value "TBR + 3C4

H

" is stored in the program counter (PC).

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The time required to start exception processing is 7 cycles.

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The address saved to the system stack as a "PC" value represents the instruction itself that caused the

undefined instruction exception. When a RETI instruction is executed, the contents of the system stack

should be rewritten with the exception processing routine so that execution will either resume from the

address of the next instruction after the instruction that caused the exception, or branch to the appropriate

processing routine.

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The following programming steps must be set up to enable the use of undefined instruction exceptions.

(1) Enter values in the interrupt vector table (defined as data).

(2) Set up the "SSP" value.

(3) Set up "TBR" value.

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Undefined instructions placed in delay slots do not generate undefined instruction exceptions. In such

cases, undefined instructions have the same operation as "NOP" instructions.