Fujitsu CM71-00101-5E User Manual
47
CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.3
Step Trace Traps
Step trace traps are traps used by debuggers. This type of trap can be created for each
individual instruction in a sequence by setting the "T" flag in the system condition code
register (SCR) in the program status (PS).
This section describes conditions for the generation, operations, program counter (PC)
values saved, and other information of step trace traps.
individual instruction in a sequence by setting the "T" flag in the system condition code
register (SCR) in the program status (PS).
This section describes conditions for the generation, operations, program counter (PC)
values saved, and other information of step trace traps.
■
Overview of Step Trace Traps
Step trace traps are traps used by debuggers. This type of trap can be created for each individual instruction
in a sequence, by setting the "T" flag in the "SCR" in the "PS".
In the execution of delayed branching instructions, step trace traps are not generated immediately after the
execution of branching. The trap is generated after execution of the instruction(s) in the delay slot.
The step trace trap can be utilized by users for systems that have not been debugged by emulators.
■
Conditions for Generation of Step Trace Traps
A step trace trap is generated when the following conditions are met.
•
The "T" flag in the "SCR" in the "PS" is set to "1".
•
The currently executing instruction is not a delayed branching instruction.
•
The CPU is not processing an "INTE" instruction or a step trace trap processing routine.
■
Step Trace Trap Operation
When a step trace trap is generated, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "S" flag in the "CCR" in the "PS".
(5) The value "TBR + 3C4
H
" is stored in "PC".
■
"PC" Values Saved for Step Trace Traps
The "PC" value saved to the system stack represents the address of the next instruction after the step trace
trap.
■
Relation of Step Trace Traps to "NMI" and External Interrupts
When the "T" flag is set to enable step trace traps, both "NMI" and external interrupts are disabled.
■
Precautionary Information for Use of Step Trace Traps
Step trace traps cannot be used in user programs involving debugging with an emulator. Note also that no
"EIT" events can be generated by "INTE" instructions when the step trace trap function is used.