Supermicro Xeon P4X-024-512K User Manual

15

Most Intel

®

 Xeon™ processor with 512 KB L2 cache front side bus signals use Assisted Gunning

Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved
noise margins and reduced ringing through low voltage swings and controlled edge rates.

 

The

processor termination voltage level is V

CC

, the operating voltage of the processor core. The use of a

termination voltage that is determined by the processor core allows better voltage scaling on the
processor front side bus. Because of the speed improvements to data and address busses, signal
integrity and platform design methods become more critical than with previous processor families.
Front side bus design guidelines are detailed in the appropriate platform design guide (refer to

The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See

 for GTLREF specifications). Termination resistors are provided on the processor silicon

and are terminated to its core voltage (V

CC

). The on-die termination resistors are a selectable

feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination
can be enabled to control reflections on the transmission line. For middle bus agents, on-die
termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating
the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to

 

 for

details on ODTEN resistor termination requirements.

Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.
See 

 for details regarding these signals.

The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
front side bus, including trace lengths, is highly recommended when designing a system. Please
refer to http://developer.intel.com to obtain the Intel

Signal Integrity Models.

For clean on-chip power distribution, the Intel

 

Xeon processor with 512 KB L2 cache has 190 V

CC

(power) and 189 V

SS

 

(ground) inputs. All V

CC

 pins must be connected to the system power plane,

while all V

SS

 pins must be connected to the system ground plane. The processor V

CC

 pins must be

supplied the voltage determined by the processor VID (Voltage ID) pins.

Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Larger bulk storage (C

BULK

), such as electrolytic capacitors, supply current during longer lasting

changes in current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running condition.