Intel 253668-032US User Manual
Vol. 3 4-23
PAGING
that do neither because they are “not present”; bit 0 (P) and bit 7 (PS) are high-
lighted because they determine how a paging-structure entry is used.
lighted because they determine how a paging-structure entry is used.
4.5 IA-32E
PAGING
A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hier-
archy of in-memory paging structures located using the contents of CR3. IA-32e
paging translates 48-bit linear addresses to 52-bit physical addresses.
IA32_EFER.LME = 1. With IA-32e paging, linear address are translated using a hier-
archy of in-memory paging structures located using the contents of CR3. IA-32e
paging translates 48-bit linear addresses to 52-bit physical addresses.
1
Although 52
6
3
3
6
2
2
6
1
1
6
0
0
5
9
9
5
8
8
5
7
7
5
6
6
5
5
5
5
4
4
5
3
3
5
2
2
5
1
1
M
1
NOTES:
1. M is an abbreviation for MAXPHYADDR.
M-1
3
2
2
3
1
1
3
0
0
2
9
9
2
8
8
2
7
7
2
6
6
2
5
5
2
4
4
2
3
3
2
2
2
2
1
1
2
0
0
1
9
9
1
8
8
1
7
7
1
6
6
1
5
5
1
4
4
1
3
3
1
2
2
1
1
1
1
0 9 8 7 6 5 4 3 2 1 0
0 9 8 7 6 5 4 3 2 1 0
Ignored
2
2. CR3 has 64 bits only on processors supporting the Intel-64 architecture. These bits are ignored with
PAE paging.
Address of page-directory-pointer table
Ignored
CR3
Reserved
3
3. Reserved fields must be 0.
Address of page directory
Ign. Rsvd.
P
C
D
P
W
T
Rs
vd 1
PDPTE:
present
Ignored
0
PDTPE:
not
present
X
D
D
Ignored
Rsvd.
Address of
2MB page frame
Reserved
P
A
T
Ign. G 1 D A
P
C
D
P
W
T
U
/
S
R
/
W
1
PDE:
2MB
page
X
D
D
Ignored
Rsvd.
Address of page table
Ign. 0
I
g
n
A
P
C
D
P
W
T
U
/
S
R
/
W
1
PDE:
page
table
Ignored
0
PDE:
not
present
X
D
D
Ignored
Rsvd.
Address of 4KB page frame
Ign. G
P
A
T
D A
P
C
D
P
W
T
U
/
S
R
/
W
1
PTE:
4KB
page
Ignored
0
PTE:
not
present
Figure 4-7. Formats of CR3 and Paging-Structure Entries with PAE Paging