Intel 253668-032US User Manual
4-32 Vol. 3
PAGING
•
If the P flag of a PML4E or a PDPTE is 1, the PS flag is reserved.
•
If the P flag and the PS flag of a PDE are both 1, bits 20:13 are reserved.
•
If IA32_EFER.NXE = 0 and the P flag of a paging-structure entry is 1, the XD flag
(bit 63) is reserved.
(bit 63) is reserved.
A reference using a linear address that is successfully translated to a physical
address is performed only if allowed by the access rights of the translation; see
Section 4.6.
Figure 4-10 gives a summary of the formats of CR3 and the IA-32e paging-structure
entries. For the paging structure entries, it identifies separately the format of entries
that map pages, those that reference other paging structures, and those that do
neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted
because they determine how a paging-structure entry is used.
address is performed only if allowed by the access rights of the translation; see
Section 4.6.
Figure 4-10 gives a summary of the formats of CR3 and the IA-32e paging-structure
entries. For the paging structure entries, it identifies separately the format of entries
that map pages, those that reference other paging structures, and those that do
neither because they are “not present”; bit 0 (P) and bit 7 (PS) are highlighted
because they determine how a paging-structure entry is used.
4.6 ACCESS
RIGHTS
There is a translation for a linear address if the processes described in Section 4.3,
Section 4.4.2, and Section 4.5 (depending upon the paging mode) completes and
produces a physical address. The accesses permitted by a translation is determined
by the access rights specified by the paging-structure entries controlling the transla-
tion.
Section 4.4.2, and Section 4.5 (depending upon the paging mode) completes and
produces a physical address. The accesses permitted by a translation is determined
by the access rights specified by the paging-structure entries controlling the transla-
tion.
1
The following items detail how paging determines access rights:
•
For accesses in supervisor mode (CPL < 3):
— Data reads.
— Data reads.
Data may be read from any linear address with a valid translation.
— Data writes.
•
If CR0.WP = 0, data may be written to any linear address with a valid
translation.
•
If CR0.WP = 1, data may be written to any linear address with a valid
translation for which the R/W flag (bit 1) is 1 in every paging-structure
entry controlling the translation.
entry controlling the translation.
— Instruction fetches.
•
For 32-bit paging or if IA32_EFER.NXE = 0, instructions may be fetched
from any linear address with a valid translation.
•
For PAE paging or IA-32e paging with IA32_EFER.NXE = 1, instructions
may be fetched from any linear address with a valid translation for which
the XD flag (bit 63) is 0 in every paging-structure entry controlling the
translation.
the XD flag (bit 63) is 0 in every paging-structure entry controlling the
translation.
•
For accesses in user mode (CPL = 3):
1. With PAE paging, the PDPTEs do not determine access rights.