Intel 253668-032US User Manual
4-48 Vol. 3
PAGING
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If software using PAE paging modifies a PDPTE, it should reload CR3 with the
register’s current value to ensure that the modified PDPTE is loaded into the
corresponding PDPTE register (see Section 4.4.1).
register’s current value to ensure that the modified PDPTE is loaded into the
corresponding PDPTE register (see Section 4.4.1).
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If the nature of the paging structures is such that a single entry may be used for
multiple purposes (see Section 4.10.2.3), software should perform invalidations
for all of these purposes. For example, if a single entry might serve as both a PDE
and PTE, it may be necessary to execute INVLPG with two (or more) linear
addresses, one that uses the entry as a PDE and one that uses it as a PTE. (Alter-
natively, software could use MOV to CR3 or MOV to CR4.)
multiple purposes (see Section 4.10.2.3), software should perform invalidations
for all of these purposes. For example, if a single entry might serve as both a PDE
and PTE, it may be necessary to execute INVLPG with two (or more) linear
addresses, one that uses the entry as a PDE and one that uses it as a PTE. (Alter-
natively, software could use MOV to CR3 or MOV to CR4.)
•
As noted in Section 4.10.1, the TLBs may subsequently contain multiple transla-
tions for the address range if software modifies the paging structures so that the
page size used for a 4-KByte range of linear addresses changes. A reference to a
linear address in the address range may use either translation.
Software wishing to prevent this uncertainty should not write to a paging-
structure entry in a way that would change, for any linear address, both the page
size and either the page frame, access rights, or other attributes. It can instead
use the following algorithm: first clear the P flag in the relevant paging-structure
entry (e.g., PDE); then invalidate any translations for the affected linear
addresses (see Section 4.10.3.2); and then modify the relevant paging-structure
entry to set the P flag and establish modified translation(s) for the new page size.
tions for the address range if software modifies the paging structures so that the
page size used for a 4-KByte range of linear addresses changes. A reference to a
linear address in the address range may use either translation.
Software wishing to prevent this uncertainty should not write to a paging-
structure entry in a way that would change, for any linear address, both the page
size and either the page frame, access rights, or other attributes. It can instead
use the following algorithm: first clear the P flag in the relevant paging-structure
entry (e.g., PDE); then invalidate any translations for the affected linear
addresses (see Section 4.10.3.2); and then modify the relevant paging-structure
entry to set the P flag and establish modified translation(s) for the new page size.
4.10.3.3 Optional Invalidation
The following items describe cases in which software may choose not to invalidate
and the potential consequences of that choice:
and the potential consequences of that choice:
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If a paging-structure entry is modified to change the P flag from 0 to 1, no inval-
idation is necessary. This is because no TLB entry or paging-structure cache entry
is created with information from a paging-structure entry in which the P flag is 0.
idation is necessary. This is because no TLB entry or paging-structure cache entry
is created with information from a paging-structure entry in which the P flag is 0.
1
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If a paging-structure entry is modified to change the accessed flag from 0 to 1,
no invalidation is necessary (assuming that an invalidation was performed the
last time the accessed flag was changed from 1 to 0). This is because no TLB
entry or paging-structure cache entry is created with information from a paging-
structure entry in which the accessed flag is 0.
no invalidation is necessary (assuming that an invalidation was performed the
last time the accessed flag was changed from 1 to 0). This is because no TLB
entry or paging-structure cache entry is created with information from a paging-
structure entry in which the accessed flag is 0.
•
If a paging-structure entry is modified to change the R/W flag from 0 to 1, failure
to perform an invalidation may result in a “spurious” page-fault exception (e.g.,
in response to an attempted write access) but no other adverse behavior. Such
an exception will occur at most once for each affected linear address (see Section
4.10.3.1).
to perform an invalidation may result in a “spurious” page-fault exception (e.g.,
in response to an attempted write access) but no other adverse behavior. Such
an exception will occur at most once for each affected linear address (see Section
4.10.3.1).
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If a paging-structure entry is modified to change the U/S flag from 0 to 1, failure
to perform an invalidation may result in a “spurious” page-fault exception (e.g.,
to perform an invalidation may result in a “spurious” page-fault exception (e.g.,
1. If it is also the case that no invalidation was performed the last time the P flag was changed
from 1 to 0, the processor may use a TLB entry or paging-structure cache entry that was cre-
ated when the P flag had earlier been 1.