Intel 253668-032US User Manual
Vol. 3 4-51
PAGING
4.11
INTERACTIONS WITH VIRTUAL-MACHINE
EXTENSIONS (VMX)
The architecture for virtual-machine extensions (VMX) includes features that interact
with paging. Section 4.11.1 discusses ways in which VMX-specific control transfers,
called VMX transitions specially affect paging. Section 4.11.2 gives an overview of
VMX features specifically designed to support address translation.
with paging. Section 4.11.1 discusses ways in which VMX-specific control transfers,
called VMX transitions specially affect paging. Section 4.11.2 gives an overview of
VMX features specifically designed to support address translation.
4.11.1 VMX
Transitions
The VMX architecture defines two control transfers called VM entries and VM exits;
collectively, these are called VMX transitions. VM entries and VM exits are
described in detail in Chapter 23 and Chapter 24, respectively, in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B. The following items
identify paging-related details:
collectively, these are called VMX transitions. VM entries and VM exits are
described in detail in Chapter 23 and Chapter 24, respectively, in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B. The following items
identify paging-related details:
•
VMX transitions modify the CR0 and CR4 registers and the IA32_EFER MSR
concurrently. For this reason, they allow transitions between paging modes that
would not otherwise be possible:
— VM entries allow transitions from IA-32e paging directly to either 32-bit
concurrently. For this reason, they allow transitions between paging modes that
would not otherwise be possible:
— VM entries allow transitions from IA-32e paging directly to either 32-bit
paging or PAE paging.
— VM exits allow transitions from either 32-bit paging or PAE paging directly to
IA-32e paging.
•
VMX transitions that result in PAE paging load the PDPTE registers (see Section
4.4.1) as follows:
— VM entries load the PDPTE registers either from the physical address being
4.4.1) as follows:
— VM entries load the PDPTE registers either from the physical address being
loaded into CR3 or from the virtual-machine control structure (VMCS); see
Section 23.3.2.4.
Section 23.3.2.4.
— VM exits load the PDPTE registers from the physical address being loaded into
•
VMX transitions invalidate the TLBs and paging-structure caches based on certain
control settings. See Section 23.3.2.5 and Section 24.5.5.
control settings. See Section 23.3.2.5 and Section 24.5.5.
4.11.2
VMX Support for Address Translation
Chapter 25, “VMX Support for Address Translation,” in the Intel® 64 and IA-32 Archi-
tectures Software Developer’s Manual, Volume 3B describe two features of the
virtual-machine extensions (VMX) that interact directly with paging. These are
virtual-processor identifiers (VPIDs) and the extended page table mechanism
(EPT).
VPIDs provide a way for software to identify to the processor the address spaces for
different “virtual processors.” The processor may use this identification to maintain
tectures Software Developer’s Manual, Volume 3B describe two features of the
virtual-machine extensions (VMX) that interact directly with paging. These are
virtual-processor identifiers (VPIDs) and the extended page table mechanism
(EPT).
VPIDs provide a way for software to identify to the processor the address spaces for
different “virtual processors.” The processor may use this identification to maintain