Intel 253668-032US User Manual
Vol. 3 8-29
MULTIPLE-PROCESSOR MANAGEMENT
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The newly established BSP broadcasts an FIPI message to “all including
self,” which the BSP and APs treat as an end of MP initialization signal.
Only the processor with its BSP flag set responds to the FIPI message. It
responds by fetching and executing the BIOS boot-strap code, beginning
at the reset vector (physical address FFFF FFF0H).
Only the processor with its BSP flag set responds to the FIPI message. It
responds by fetching and executing the BIOS boot-strap code, beginning
at the reset vector (physical address FFFF FFF0H).
5. As part of the boot-strap code, the BSP creates an ACPI table and an MP table and
adds its initial APIC ID to these tables as appropriate.
6. At the end of the boot-strap procedure, the BSP sets a processor counter to 1,
then broadcasts a SIPI message to all the APs in the system. Here, the SIPI
message contains a vector to the BIOS AP initialization code (at 000VV000H,
where VV is the vector contained in the SIPI message).
message contains a vector to the BIOS AP initialization code (at 000VV000H,
where VV is the vector contained in the SIPI message).
7. The first action of the AP initialization code is to set up a race (among the APs) to
a BIOS initialization semaphore. The first AP to the semaphore begins executing
the initialization code. (See Section 8.4.4, “MP Initialization Example,” for
semaphore implementation details.) As part of the AP initialization procedure,
the AP adds its APIC ID number to the ACPI and MP tables as appropriate and
increments the processor counter by 1. At the completion of the initialization
procedure, the AP executes a CLI instruction and halts itself.
the initialization code. (See Section 8.4.4, “MP Initialization Example,” for
semaphore implementation details.) As part of the AP initialization procedure,
the AP adds its APIC ID number to the ACPI and MP tables as appropriate and
increments the processor counter by 1. At the completion of the initialization
procedure, the AP executes a CLI instruction and halts itself.
8. When each of the APs has gained access to the semaphore and executed the AP
initialization code, the BSP establishes a count for the number of processors
connected to the system bus, completes executing the BIOS boot-strap code,
and then begins executing operating-system boot-strap and start-up code.
connected to the system bus, completes executing the BIOS boot-strap code,
and then begins executing operating-system boot-strap and start-up code.
9. While the BSP is executing operating-system boot-strap and start-up code, the
APs remain in the halted state. In this state they will respond only to INITs, NMIs,
and SMIs. They will also respond to snoops and to assertions of the STPCLK# pin.
and SMIs. They will also respond to snoops and to assertions of the STPCLK# pin.
The following section gives an example (with code) of the MP initialization protocol
for multiple Intel Xeon processors operating in an MP configuration.
Appendix B, “Model-Specific Registers (MSRs),” describes how to program the
LINT[0:1] pins of the processor’s local APICs after an MP configuration has been
completed.
for multiple Intel Xeon processors operating in an MP configuration.
Appendix B, “Model-Specific Registers (MSRs),” describes how to program the
LINT[0:1] pins of the processor’s local APICs after an MP configuration has been
completed.
8.4.4
MP Initialization Example
The following example illustrates the use of the MP initialization protocol used to
initialize processors in an MP system after the BSP and APs have been established.
The code runs on Intel 64 or IA-32 processors that use a protocol. This includes P6
Family processors, Pentium 4 processors, Intel Core Duo, Intel Core 2 Duo and Intel
Xeon processors.
The following constants and data definitions are used in the accompanying
initialize processors in an MP system after the BSP and APs have been established.
The code runs on Intel 64 or IA-32 processors that use a protocol. This includes P6
Family processors, Pentium 4 processors, Intel Core Duo, Intel Core 2 Duo and Intel
Xeon processors.
The following constants and data definitions are used in the accompanying
code examples. They are based on the addresses of the APIC registers defined in
Table 10-1.
Table 10-1.
ICR_LOW
EQU 0FEE00300H