Intel 253668-032US User Manual
8-46 Vol. 3
MULTIPLE-PROCESSOR MANAGEMENT
8.8 MULTI-CORE
ARCHITECTURE
This section describes the architecture of Intel 64 and IA-32 processors supporting
dual-core and quad-core technology. The discussion is applicable to the Intel Pentium
processor Extreme Edition, Pentium D, Intel Core Duo, Intel Core 2 Duo, Dual-core
Intel Xeon processor, Intel Core 2 Quad processors, and quad-core Intel Xeon
processors. Features vary across different microarchitectures and are detectable
using CPUID.
In general, each processor core has dedicated microarchitectural resources identical
to a single-processor implementation of the underlying microarchitecture without
hardware multi-threading capability. Each logical processor in a dual-core processor
(whether supporting Intel Hyper-Threading Technology or not) has its own APIC
functionality, PAT, machine check architecture, debug registers and extensions. Each
logical processor handles serialization instructions or self-modifying code on its own.
Memory order is handled the same way as in Intel Hyper-Threading Technology.
The topology of the cache hierarchy (with respect to whether a given cache level is
shared by one or more processor cores or by all logical processors in the physical
package) depends on the processor implementation. Software must use the deter-
ministic cache parameter leaf of CPUID instruction to discover the cache-sharing
topology between the logical processors in a multi-threading environment.
dual-core and quad-core technology. The discussion is applicable to the Intel Pentium
processor Extreme Edition, Pentium D, Intel Core Duo, Intel Core 2 Duo, Dual-core
Intel Xeon processor, Intel Core 2 Quad processors, and quad-core Intel Xeon
processors. Features vary across different microarchitectures and are detectable
using CPUID.
In general, each processor core has dedicated microarchitectural resources identical
to a single-processor implementation of the underlying microarchitecture without
hardware multi-threading capability. Each logical processor in a dual-core processor
(whether supporting Intel Hyper-Threading Technology or not) has its own APIC
functionality, PAT, machine check architecture, debug registers and extensions. Each
logical processor handles serialization instructions or self-modifying code on its own.
Memory order is handled the same way as in Intel Hyper-Threading Technology.
The topology of the cache hierarchy (with respect to whether a given cache level is
shared by one or more processor cores or by all logical processors in the physical
package) depends on the processor implementation. Software must use the deter-
ministic cache parameter leaf of CPUID instruction to discover the cache-sharing
topology between the logical processors in a multi-threading environment.
8.8.1
Logical Processor Support
The topological composition of processor cores and logical processors in a multi-core
processor can be discovered using CPUID. Within each processor core, one or more
logical processors may be available.
System software must follow the requirement MP initialization sequences (see
Section 8.4, “Multiple-Processor (MP) Initialization”) to recognize and enable logical
processors. At runtime, software can enumerate those logical processors enabled by
system software to identify the topological relationships between these logical
processors. (See Section 8.9.5, “Identifying Topological Relationships in a MP
System”).
processor can be discovered using CPUID. Within each processor core, one or more
logical processors may be available.
System software must follow the requirement MP initialization sequences (see
Section 8.4, “Multiple-Processor (MP) Initialization”) to recognize and enable logical
processors. At runtime, software can enumerate those logical processors enabled by
system software to identify the topological relationships between these logical
processors. (See Section 8.9.5, “Identifying Topological Relationships in a MP
System”).
8.8.2
Memory Type Range Registers (MTRR)
MTRR is shared between two logical processors sharing a processor core if the phys-
ical processor supports Intel Hyper-Threading Technology. MTRR is not shared
between logical processors located in different cores or different physical packages.
The Intel 64 and IA-32 architectures require that all logical processors in an MP
system use an identical MTRR memory map. This gives software a consistent view of
memory, independent of the processor on which it is running.
See Section 11.11, “Memory Type Range Registers (MTRRs).”
ical processor supports Intel Hyper-Threading Technology. MTRR is not shared
between logical processors located in different cores or different physical packages.
The Intel 64 and IA-32 architectures require that all logical processors in an MP
system use an identical MTRR memory map. This gives software a consistent view of
memory, independent of the processor on which it is running.
See Section 11.11, “Memory Type Range Registers (MTRRs).”