Intel 253668-032US User Manual
Vol. 3 9-1
CHAPTER 9
PROCESSOR MANAGEMENT AND INITIALIZATION
This chapter describes the facilities provided for managing processor wide functions
and for initializing the processor. The subjects covered include: processor initializa-
tion, x87 FPU initialization, processor configuration, feature determination, mode
switching, the MSRs (in the Pentium, P6 family, Pentium 4, and Intel Xeon proces-
sors), and the MTRRs (in the P6 family, Pentium 4, and Intel Xeon processors).
and for initializing the processor. The subjects covered include: processor initializa-
tion, x87 FPU initialization, processor configuration, feature determination, mode
switching, the MSRs (in the Pentium, P6 family, Pentium 4, and Intel Xeon proces-
sors), and the MTRRs (in the P6 family, Pentium 4, and Intel Xeon processors).
9.1 INITIALIZATION
OVERVIEW
Following power-up or an assertion of the RESET# pin, each processor on the system
bus performs a hardware initialization of the processor (known as a hardware reset)
and an optional built-in self-test (BIST). A hardware reset sets each processor’s
registers to a known state and places the processor in real-address mode. It also
invalidates the internal caches, translation lookaside buffers (TLBs) and the branch
target buffer (BTB). At this point, the action taken depends on the processor family:
bus performs a hardware initialization of the processor (known as a hardware reset)
and an optional built-in self-test (BIST). A hardware reset sets each processor’s
registers to a known state and places the processor in real-address mode. It also
invalidates the internal caches, translation lookaside buffers (TLBs) and the branch
target buffer (BTB). At this point, the action taken depends on the processor family:
•
Pentium 4 and Intel Xeon processors — All the processors on the system bus
(including a single processor in a uniprocessor system) execute the multiple
processor (MP) initialization protocol. The processor that is selected through this
protocol as the bootstrap processor (BSP) then immediately starts executing
software-initialization code in the current code segment beginning at the offset in
the EIP register. The application (non-BSP) processors (APs) go into a Wait For
Startup IPI (SIPI) state while the BSP is executing initialization code. See Section
8.4, “Multiple-Processor (MP) Initialization,” for more details. Note that in a
uniprocessor system, the single Pentium 4 or Intel Xeon processor automatically
becomes the BSP.
(including a single processor in a uniprocessor system) execute the multiple
processor (MP) initialization protocol. The processor that is selected through this
protocol as the bootstrap processor (BSP) then immediately starts executing
software-initialization code in the current code segment beginning at the offset in
the EIP register. The application (non-BSP) processors (APs) go into a Wait For
Startup IPI (SIPI) state while the BSP is executing initialization code. See Section
8.4, “Multiple-Processor (MP) Initialization,” for more details. Note that in a
uniprocessor system, the single Pentium 4 or Intel Xeon processor automatically
becomes the BSP.
•
P6 family processors — The action taken is the same as for the Pentium 4 and
Intel Xeon processors (as described in the previous paragraph).
Intel Xeon processors (as described in the previous paragraph).
•
Pentium processors — In either a single- or dual- processor system, a single
Pentium processor is always pre-designated as the primary processor. Following
a reset, the primary processor behaves as follows in both single- and dual-
processor systems. Using the dual-processor (DP) ready initialization protocol,
the primary processor immediately starts executing software-initialization code
in the current code segment beginning at the offset in the EIP register. The
secondary processor (if there is one) goes into a halt state.
Pentium processor is always pre-designated as the primary processor. Following
a reset, the primary processor behaves as follows in both single- and dual-
processor systems. Using the dual-processor (DP) ready initialization protocol,
the primary processor immediately starts executing software-initialization code
in the current code segment beginning at the offset in the EIP register. The
secondary processor (if there is one) goes into a halt state.
•
Intel486 processor — The primary processor (or single processor in a unipro-
cessor system) immediately starts executing software-initialization code in the
current code segment beginning at the offset in the EIP register. (The Intel486
does not automatically execute a DP or MP initialization protocol to determine
which processor is the primary processor.)
cessor system) immediately starts executing software-initialization code in the
current code segment beginning at the offset in the EIP register. (The Intel486
does not automatically execute a DP or MP initialization protocol to determine
which processor is the primary processor.)