Intel 253668-032US User Manual
11-24 Vol. 3
MEMORY CACHE CONTROL
11.5.3 Preventing
Caching
To disable the L1, L2, and L3 caches after they have been enabled and have received
cache fills, perform the following steps:
1. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and
cache fills, perform the following steps:
1. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and
the NW flag to 0.
2. Flush all caches using the WBINVD instruction.
3. Disable the MTRRs and set the default memory type to uncached or set all MTRRs
3. Disable the MTRRs and set the default memory type to uncached or set all MTRRs
for the uncached memory type (see the discussion of the discussion of the TYPE
field and the E flag in Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR”).
field and the E flag in Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR”).
The caches must be flushed (step 2) after the CD flag is set to insure system memory
coherency. If the caches are not flushed, cache hits on reads will still occur and data
will be read from valid cache lines.
The intent of the three separate steps listed above address three distinct require-
ments: (i) discontinue new data replacing existing data in the cache (ii) ensure data
already in the cache are evicted to memory, (iii) ensure subsequent memory refer-
ences observe UC memory type semantics. Different processor implementation of
caching control hardware may allow some variation of software implementation of
these three requirements. See note below.
coherency. If the caches are not flushed, cache hits on reads will still occur and data
will be read from valid cache lines.
The intent of the three separate steps listed above address three distinct require-
ments: (i) discontinue new data replacing existing data in the cache (ii) ensure data
already in the cache are evicted to memory, (iii) ensure subsequent memory refer-
ences observe UC memory type semantics. Different processor implementation of
caching control hardware may allow some variation of software implementation of
these three requirements. See note below.
NOTES
Setting the CD flag in control register CR0 modifies the processor’s
caching behaviour as indicated in Table 11-5, but setting the CD flag
alone may not be sufficient across all processor families to force the
effective memory type for all physical memory to be UC nor does it
force strict memory ordering, due to hardware implementation
variations across different processor families. To force the UC
memory type and strict memory ordering on all of physical memory,
it is sufficient to either program the MTRRs for all physical memory to
be UC memory type or disable all MTRRs.
For the Pentium 4 and Intel Xeon processors, after the sequence of
steps given above has been executed, the cache lines containing the
code between the end of the WBINVD instruction and before the
MTRRS have actually been disabled may be retained in the cache
hierarchy. Here, to remove code from the cache completely, a second
WBINVD instruction must be executed after the MTRRs have been
disabled.
For Intel Atom processors, setting the CD flag forces all physical
memory to observe UC semantics (without requiring memory type of
physical memory to be set explicitly). Consequently, software does
not need to issue a second WBINVD as some other processor
generations might require.
caching behaviour as indicated in Table 11-5, but setting the CD flag
alone may not be sufficient across all processor families to force the
effective memory type for all physical memory to be UC nor does it
force strict memory ordering, due to hardware implementation
variations across different processor families. To force the UC
memory type and strict memory ordering on all of physical memory,
it is sufficient to either program the MTRRs for all physical memory to
be UC memory type or disable all MTRRs.
For the Pentium 4 and Intel Xeon processors, after the sequence of
steps given above has been executed, the cache lines containing the
code between the end of the WBINVD instruction and before the
MTRRS have actually been disabled may be retained in the cache
hierarchy. Here, to remove code from the cache completely, a second
WBINVD instruction must be executed after the MTRRs have been
disabled.
For Intel Atom processors, setting the CD flag forces all physical
memory to observe UC semantics (without requiring memory type of
physical memory to be set explicitly). Consequently, software does
not need to issue a second WBINVD as some other processor
generations might require.