Intel 253668-032US User Manual
Vol. 3 14-9
POWER AND THERMAL MANAGEMENT
Software can program the lowest four bits of IA32_ENERGY_PERF_BIAS MSR with a
value from 0 - 15. The values represent a sliding scale, where a value of 0 (the
default reset value) corresponds to a hint preference for highest performance and a
value of 15 corresponds to the maximum energy savings. A value of 7 roughly trans-
lates into a hint to balance performance with energy consumption
value from 0 - 15. The values represent a sliding scale, where a value of 0 (the
default reset value) corresponds to a hint preference for highest performance and a
value of 15 corresponds to the maximum energy savings. A value of 7 roughly trans-
lates into a hint to balance performance with energy consumption
The layout of IA32_ENERGY_PERF_BIAS is shown in Figure 14-4. The scope of
IA32_ENERGY_PERF_BIAS is per logical processor, which means that each of the
logical processors in the package can be programmed with a different value. This
may be especially important in virtualization scenarios, where the performance /
energy requirements of one logical processor may differ from the other. Conflicting
"hints" from various logical processors at higher hierarchy level will be resolved in
favor of performance over energy savings.
Software can use whatever criteria it sees fit to program the MSR with the appro-
priate value. However, the value only serves as a hint to the hardware and the actual
impact on performance and energy savings is model specific.
IA32_ENERGY_PERF_BIAS is per logical processor, which means that each of the
logical processors in the package can be programmed with a different value. This
may be especially important in virtualization scenarios, where the performance /
energy requirements of one logical processor may differ from the other. Conflicting
"hints" from various logical processors at higher hierarchy level will be resolved in
favor of performance over energy savings.
Software can use whatever criteria it sees fit to program the MSR with the appro-
priate value. However, the value only serves as a hint to the hardware and the actual
impact on performance and energy savings is model specific.
14.4
MWAIT EXTENSIONS FOR ADVANCED POWER
MANAGEMENT
IA-32 processors may support a number of C-states
1
that reduce power consumption
for inactive states. Intel Core Solo and Intel Core Duo processors support both
deeper C-state and MWAIT extensions that can be used by OS to implement power
management policy.
Software should use CPUID to discover if a target processor supports the enumera-
tion of MWAIT extensions. If CPUID.05H.ECX[Bit 0] = 1, the target processor
supports MWAIT extensions and their enumeration (see Chapter 3, “Instruction Set
deeper C-state and MWAIT extensions that can be used by OS to implement power
management policy.
Software should use CPUID to discover if a target processor supports the enumera-
tion of MWAIT extensions. If CPUID.05H.ECX[Bit 0] = 1, the target processor
supports MWAIT extensions and their enumeration (see Chapter 3, “Instruction Set
Figure 14-4. IA32_ENERGY_PERF_BIAS Register
1. The processor-specific C-states defined in MWAIT extensions can map to ACPI defined C-state
types (C0, C1, C2, C3). The mapping relationship depends on the definition of a C-state by proces-
sor implementation and is exposed to OSPM by the BIOS using the ACPI defined _CST table.
63
0
Reserved
Energy Policy Preference Hint
4 3