Intel 253668-032US User Manual
14-16 Vol. 3
POWER AND THERMAL MANAGEMENT
interrupt enable flags in the IA32_THERM_INTERRUPT MSR are cleared (interrupts
are disabled) and the thermal LVT entry is set to mask interrupts. This interrupt
should be handled either by the operating system or system management mode
(SMM) code.
Note that the operation of the thermal monitoring mechanism has no effect upon the
clock rate of the processor's internal high-resolution timer (time stamp counter).
are disabled) and the thermal LVT entry is set to mask interrupts. This interrupt
should be handled either by the operating system or system management mode
(SMM) code.
Note that the operation of the thermal monitoring mechanism has no effect upon the
clock rate of the processor's internal high-resolution timer (time stamp counter).
14.5.2.6 Adaptive Thermal Monitor
The Intel Core 2 Duo processor family supports enhanced thermal management
mechanism, referred to as Adaptive Thermal Monitor (Adaptive TM).
Unlike TM2, Adaptive TM is not limited to one TM2 transition target. During a thermal
trip event, Adaptive TM (if enabled) selects an optimal target operating point based
on whether or not the current operating point has effectively cooled the processor.
Similar to TM2, Adaptive TM is enable by BIOS. The BIOS is required to test the TM1
and TM2 feature flags and enable all available thermal control mechanisms (including
Adaptive TM) at platform initiation.
Adaptive TM is available only to a subset of processors that support TM2.
In each chip-multiprocessing (CMP) silicon die, each core has a unique thermal
sensor that triggers independently. These thermal sensor can trigger TM1 or TM2
transitions in the same manner as described in Section 14.5.2.1 and Section
14.5.2.2. The trip point of the thermal sensor is not programmable by software since
it is set during the fabrication of the processor.
Each thermal sensor in a processor core may be triggered independently to engage
thermal management features. In Adaptive TM, both cores will transition to a lower
frequency and/or lower voltage level if one sensor is triggered.
Triggering of this sensor is visible to software via the thermal interrupt LVT entry in
the local APIC of a given core.
mechanism, referred to as Adaptive Thermal Monitor (Adaptive TM).
Unlike TM2, Adaptive TM is not limited to one TM2 transition target. During a thermal
trip event, Adaptive TM (if enabled) selects an optimal target operating point based
on whether or not the current operating point has effectively cooled the processor.
Similar to TM2, Adaptive TM is enable by BIOS. The BIOS is required to test the TM1
and TM2 feature flags and enable all available thermal control mechanisms (including
Adaptive TM) at platform initiation.
Adaptive TM is available only to a subset of processors that support TM2.
In each chip-multiprocessing (CMP) silicon die, each core has a unique thermal
sensor that triggers independently. These thermal sensor can trigger TM1 or TM2
transitions in the same manner as described in Section 14.5.2.1 and Section
14.5.2.2. The trip point of the thermal sensor is not programmable by software since
it is set during the fabrication of the processor.
Each thermal sensor in a processor core may be triggered independently to engage
thermal management features. In Adaptive TM, both cores will transition to a lower
frequency and/or lower voltage level if one sensor is triggered.
Triggering of this sensor is visible to software via the thermal interrupt LVT entry in
the local APIC of a given core.
14.5.3 Software
Controlled Clock Modulation
Pentium 4, Intel Xeon and Pentium M processors also support software-controlled
clock modulation. This provides a means for operating systems to implement a power
management policy to reduce the power consumption of the processor. Here, the
stop-clock duty cycle is controlled by software through the
IA32_CLOCK_MODULATION MSR (see Figure 14-10).
clock modulation. This provides a means for operating systems to implement a power
management policy to reduce the power consumption of the processor. Here, the
stop-clock duty cycle is controlled by software through the
IA32_CLOCK_MODULATION MSR (see Figure 14-10).