Intel 253668-032US User Manual
Vol. 3 15-29
MACHINE-CHECK ARCHITECTURE
(* enables all MCA features *)
FI
(* Determine number of error-reporting banks supported *)
COUNT
←
IA32_MCG_CAP.Count;
MAX_BANK_NUMBER
←
COUNT - 1;
IF (Processor Family is 6H and Processor EXTMODEL:MODEL is less than 1AH)
THEN
THEN
(* Enable logging of all errors except for MC0_CTL register *)
FOR error-reporting banks (1 through MAX_BANK_NUMBER)
DO
DO
IA32_MCi_CTL
←
0FFFFFFFFFFFFFFFFH;
OD
ELSE
(* Enable logging of all errors including MC0_CTL register *)
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
IA32_MCi_CTL
←
0FFFFFFFFFFFFFFFFH;
OD
FI
(* BIOS clears all errors only on power-on reset *)
IF (BIOS detects Power-on reset)
IF (BIOS detects Power-on reset)
THEN
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
DO
IA32_MCi_STATUS
←
0;
OD
ELSE
FOR error-reporting banks (0 through MAX_BANK_NUMBER)
DO
(Optional for BIOS and OS) Log valid errors
(OS only) IA32_MCi_STATUS
(OS only) IA32_MCi_STATUS
←
0;
OD
FI
FI
Setup the Machine Check Exception (#MC) handler for vector 18 in IDT
Set the MCE bit (bit 6) in CR4 register to enable Machine-Check Exceptions
FI
15.9
INTERPRETING THE MCA ERROR CODES
When the processor detects a machine-check error condition, it writes a 16-
bit error code to the MCA error code field of one of the IA32_MCi_STATUS
registers and sets the VAL (valid) flag in that register. The processor may