Intel 253668-032US User Manual
Vol. 3 2-9
SYSTEM ARCHITECTURE OVERVIEW
2.1.6 System
Registers
To assist in initializing the processor and controlling system operations, the system
architecture provides system flags in the EFLAGS register and several system
registers:
architecture provides system flags in the EFLAGS register and several system
registers:
•
The system flags and IOPL field in the EFLAGS register control task and mode
switching, interrupt handling, instruction tracing, and access rights. See also:
Section 2.3, “System Flags and Fields in the EFLAGS Register.”
switching, interrupt handling, instruction tracing, and access rights. See also:
Section 2.3, “System Flags and Fields in the EFLAGS Register.”
•
The control registers (CR0, CR2, CR3, and CR4) contain a variety of flags and
data fields for controlling system-level operations. Other flags in these registers
are used to indicate support for specific processor capabilities within the
operating system or executive. See also: Section 2.5, “Control Registers.”
data fields for controlling system-level operations. Other flags in these registers
are used to indicate support for specific processor capabilities within the
operating system or executive. See also: Section 2.5, “Control Registers.”
•
The debug registers (not shown in Figure 2-1) allow the setting of breakpoints for
use in debugging programs and systems software. See also: Chapter 16,
“Debugging, Profiling Branches and Time-Stamp Counter.”
use in debugging programs and systems software. See also: Chapter 16,
“Debugging, Profiling Branches and Time-Stamp Counter.”
•
The GDTR, LDTR, and IDTR registers contain the linear addresses and sizes
(limits) of their respective tables. See also: Section 2.4, “Memory-Management
Registers.”
(limits) of their respective tables. See also: Section 2.4, “Memory-Management
Registers.”
•
The task register contains the linear address and size of the TSS for the current
task. See also: Section 2.4, “Memory-Management Registers.”
task. See also: Section 2.4, “Memory-Management Registers.”
•
Model-specific registers (not shown in Figure 2-1).
The model-specific registers (MSRs) are a group of registers available primarily to
operating-system or executive procedures (that is, code running at privilege level 0).
These registers control items such as the debug extensions, the performance-moni-
toring counters, the machine- check architecture, and the memory type ranges
(MTRRs).
The number and function of these registers varies among different members of the
Intel 64 and IA-32 processor families. See also: Section 9.4, “Model-Specific Regis-
ters (MSRs),” and Appendix B, “Model-Specific Registers (MSRs).”
Most systems restrict access to system registers (other than the EFLAGS register) by
application programs. Systems can be designed, however, where all programs and
procedures run at the most privileged level (privilege level 0). In such a case, appli-
cation programs would be allowed to modify the system registers.
operating-system or executive procedures (that is, code running at privilege level 0).
These registers control items such as the debug extensions, the performance-moni-
toring counters, the machine- check architecture, and the memory type ranges
(MTRRs).
The number and function of these registers varies among different members of the
Intel 64 and IA-32 processor families. See also: Section 9.4, “Model-Specific Regis-
ters (MSRs),” and Appendix B, “Model-Specific Registers (MSRs).”
Most systems restrict access to system registers (other than the EFLAGS register) by
application programs. Systems can be designed, however, where all programs and
procedures run at the most privileged level (privilege level 0). In such a case, appli-
cation programs would be allowed to modify the system registers.
2.1.6.1
System Registers in IA-32e Mode
In IA-32e mode, the four system-descriptor-table registers (GDTR, IDTR, LDTR, and
TR) are expanded in hardware to hold 64-bit base addresses. EFLAGS becomes the
64-bit RFLAGS register. CR0-CR4 are expanded to 64 bits. CR8 becomes available.
CR8 provides read-write access to the task priority register (TPR) so that the oper-
ating system can control the priority classes of external interrupts.
In 64-bit mode, debug registers DR0–DR7 are 64 bits. In compatibility mode,
address-matching in DR0-DR3 is also done at 64-bit granularity.
TR) are expanded in hardware to hold 64-bit base addresses. EFLAGS becomes the
64-bit RFLAGS register. CR0-CR4 are expanded to 64 bits. CR8 becomes available.
CR8 provides read-write access to the task priority register (TPR) so that the oper-
ating system can control the priority classes of external interrupts.
In 64-bit mode, debug registers DR0–DR7 are 64 bits. In compatibility mode,
address-matching in DR0-DR3 is also done at 64-bit granularity.