Intel 253668-032US User Manual
Vol. 3 17-15
8086 EMULATION
execution sequence after verifying that it was entered as a result of a HLT
execution.
execution.
See Section 17.3, “Interrupt and Exception Handling in Virtual-8086 Mode”, for infor-
mation on leaving virtual-8086 mode to handle an interrupt or exception generated
in virtual-8086 mode.
mation on leaving virtual-8086 mode to handle an interrupt or exception generated
in virtual-8086 mode.
17.2.7 Sensitive
Instructions
When an IA-32 processor is running in virtual-8086 mode, the CLI, STI, PUSHF, POPF,
INT n, and IRET instructions are sensitive to IOPL. The IN, INS, OUT, and OUTS
instructions, which are sensitive to IOPL in protected mode, are not sensitive in
virtual-8086 mode.
The CPL is always 3 while running in virtual-8086 mode; if the IOPL is less than 3, an
attempt to use the IOPL-sensitive instructions listed above triggers a general-protec-
tion exception (#GP). These instructions are sensitive to IOPL to give the virtual-
8086 monitor a chance to emulate the facilities they affect.
INT n, and IRET instructions are sensitive to IOPL. The IN, INS, OUT, and OUTS
instructions, which are sensitive to IOPL in protected mode, are not sensitive in
virtual-8086 mode.
The CPL is always 3 while running in virtual-8086 mode; if the IOPL is less than 3, an
attempt to use the IOPL-sensitive instructions listed above triggers a general-protec-
tion exception (#GP). These instructions are sensitive to IOPL to give the virtual-
8086 monitor a chance to emulate the facilities they affect.
17.2.8
Virtual-8086 Mode I/O
Many 8086 programs written for non-multitasking systems directly access I/O ports.
This practice may cause problems in a multitasking environment. If more than one
program accesses the same port, they may interfere with each other. Most multi-
tasking systems require application programs to access I/O ports through the oper-
ating system. This results in simplified, centralized control.
The processor provides I/O protection for creating I/O that is compatible with the
environment and transparent to 8086 programs. Designers may take any of several
possible approaches to protecting I/O ports:
This practice may cause problems in a multitasking environment. If more than one
program accesses the same port, they may interfere with each other. Most multi-
tasking systems require application programs to access I/O ports through the oper-
ating system. This results in simplified, centralized control.
The processor provides I/O protection for creating I/O that is compatible with the
environment and transparent to 8086 programs. Designers may take any of several
possible approaches to protecting I/O ports:
•
Protect the I/O address space and generate exceptions for all attempts to
perform I/O directly.
perform I/O directly.
•
Let the 8086 program perform I/O directly.
•
Generate exceptions on attempts to access specific I/O ports.
•
Generate exceptions on attempts to access specific memory-mapped I/O ports.
The method of controlling access to I/O ports depends upon whether they are
I/O-port mapped or memory mapped.
I/O-port mapped or memory mapped.
17.2.8.1 I/O-Port-Mapped I/O
The I/O permission bit map in the TSS can be used to generate exceptions on
attempts to access specific I/O port addresses. The I/O permission bit map of each
virtual-8086-mode task determines which I/O addresses generate exceptions for
that task. Because each task may have a different I/O permission bit map, the
addresses that generate exceptions for one task may be different from the addresses
attempts to access specific I/O port addresses. The I/O permission bit map of each
virtual-8086-mode task determines which I/O addresses generate exceptions for
that task. Because each task may have a different I/O permission bit map, the
addresses that generate exceptions for one task may be different from the addresses