Intel 253668-032US User Manual
Vol. 3 19-7
ARCHITECTURE COMPATIBILITY
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Single-bit instructions.
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Bit scan instructions.
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Double-shift instructions.
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Byte set on condition instruction.
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Move with sign/zero extension.
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Generalized multiply instruction.
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MOV to and from control registers.
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MOV to and from test registers (now obsolete).
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MOV to and from debug registers.
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RSM (resume from SMM). This instruction was introduced in the Intel386 SL and
Intel486 SL processors.
Intel486 SL processors.
The following instructions were added in the Intel 387 math coprocessor:
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FPREM1.
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FUCOM, FUCOMP, and FUCOMPP.
19.14 OBSOLETE
INSTRUCTIONS
The MOV to and from test registers instructions were removed from the Pentium
processor and future IA-32 processors. Execution of these instructions generates an
invalid-opcode exception (#UD).
processor and future IA-32 processors. Execution of these instructions generates an
invalid-opcode exception (#UD).
19.15 UNDEFINED
OPCODES
All new instructions defined for IA-32 processors use binary encodings that were
reserved on earlier-generation processors. Attempting to execute a reserved opcode
always results in an invalid-opcode (#UD) exception being generated. Consequently,
programs that execute correctly on earlier-generation processors cannot erroneously
execute these instructions and thereby produce unexpected results when executed
on later IA-32 processors.
reserved on earlier-generation processors. Attempting to execute a reserved opcode
always results in an invalid-opcode (#UD) exception being generated. Consequently,
programs that execute correctly on earlier-generation processors cannot erroneously
execute these instructions and thereby produce unexpected results when executed
on later IA-32 processors.
19.16 NEW FLAGS IN THE EFLAGS REGISTER
The section titled “EFLAGS Register” in Chapter 3, “Basic Execution Environment,” of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,
shows the configuration of flags in the EFLAGS register for the P6 family processors.
No new flags have been added to this register in the P6 family processors. The flags
added to this register in the Pentium and Intel486 processors are described in the
following sections.
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,
shows the configuration of flags in the EFLAGS register for the P6 family processors.
No new flags have been added to this register in the P6 family processors. The flags
added to this register in the Pentium and Intel486 processors are described in the
following sections.