Intel 253668-032US User Manual
19-14 Vol. 3
ARCHITECTURE COMPATIBILITY
The difference is apparent only to the exception handler. This difference is for IEEE
Standard 754 compatibility.
Standard 754 compatibility.
19.18.6.3 Numeric Underflow Exception (#U)
When the underflow exception is masked on the 32-bit x87 FPUs, the underflow
exception is signaled when both the result is tiny and denormalization results in a
loss of accuracy. When the underflow exception is unmasked and the instruction is
supposed to store the result on the stack, the significand is rounded to the appro-
priate precision (according to the PC flag in the FPU control word, for those instruc-
tions controlled by PC, otherwise to extended precision), after adjusting the
exponent.
When the underflow exception is masked on the 16-bit IA-32 math coprocessors and
rounding is toward 0, the underflow exception flag is raised on a tiny result, regard-
less of loss of accuracy. When the underflow exception is not masked and the desti-
nation is the stack, the significand is not rounded, but instead is left as is.
When the underflow exception is masked, this difference has no impact on existing
software. The underflow exception occurs less often when rounding is toward 0.
When the underflow exception not masked. A program running on a 32-bit x87 FPU
produces a different result during underflow conditions than on a 16-bit IA-32 math
coprocessor if the result is stored on the stack. The difference is only in the least
significant bit of the significand and is apparent only to the exception handler.
exception is signaled when both the result is tiny and denormalization results in a
loss of accuracy. When the underflow exception is unmasked and the instruction is
supposed to store the result on the stack, the significand is rounded to the appro-
priate precision (according to the PC flag in the FPU control word, for those instruc-
tions controlled by PC, otherwise to extended precision), after adjusting the
exponent.
When the underflow exception is masked on the 16-bit IA-32 math coprocessors and
rounding is toward 0, the underflow exception flag is raised on a tiny result, regard-
less of loss of accuracy. When the underflow exception is not masked and the desti-
nation is the stack, the significand is not rounded, but instead is left as is.
When the underflow exception is masked, this difference has no impact on existing
software. The underflow exception occurs less often when rounding is toward 0.
When the underflow exception not masked. A program running on a 32-bit x87 FPU
produces a different result during underflow conditions than on a 16-bit IA-32 math
coprocessor if the result is stored on the stack. The difference is only in the least
significant bit of the significand and is apparent only to the exception handler.
19.18.6.4 Exception Precedence
There is no difference in the precedence of the denormal-operand exception on the
32-bit x87 FPUs, whether it be masked or not. When the denormal-operand excep-
tion is not masked on the 16-bit IA-32 math coprocessors, it takes precedence over
all other exceptions. This difference causes no impact on existing software, but some
unneeded normalization of denormalized operands is prevented on the Intel486
processor and Intel 387 math coprocessor.
32-bit x87 FPUs, whether it be masked or not. When the denormal-operand excep-
tion is not masked on the 16-bit IA-32 math coprocessors, it takes precedence over
all other exceptions. This difference causes no impact on existing software, but some
unneeded normalization of denormalized operands is prevented on the Intel486
processor and Intel 387 math coprocessor.
19.18.6.5 CS and EIP For FPU Exceptions
On the Intel 32-bit x87 FPUs, the values from the CS and EIP registers saved for
floating-point exceptions point to any prefixes that come before the floating-point
instruction. On the 8087 math coprocessor, the saved CS and IP registers points to
the floating-point instruction.
floating-point exceptions point to any prefixes that come before the floating-point
instruction. On the 8087 math coprocessor, the saved CS and IP registers points to
the floating-point instruction.
19.18.6.6 FPU Error Signals
The floating-point error signals to the P6 family, Pentium, and Intel486 processors do
not pass through an interrupt controller; an INT# signal from an Intel 387, Intel 287
or 8087 math coprocessors does. If an 8086 processor uses another exception for
not pass through an interrupt controller; an INT# signal from an Intel 387, Intel 287
or 8087 math coprocessors does. If an 8086 processor uses another exception for