Intel 253668-032US User Manual
Vol. 3 2-31
SYSTEM ARCHITECTURE OVERVIEW
Instructions),” for a detailed explanation of the function and use of this
instruction.
2.7.3
Loading and Storing Debug Registers
Internal debugging facilities in the processor are controlled by a set of 8 debug regis-
ters (DR0-DR7). The MOV instruction allows setup data to be loaded to and stored
from these registers.
On processors that support Intel 64 architecture, debug registers DR0-DR7 are 64
bits. In 32-bit modes and compatibility mode, writes to a debug register fill the upper
32 bits with zeros. Reads return the lower 32 bits. In 64-bit mode, the upper 32 bits
of DR6-DR7 are reserved and must be written with zeros. Writing one to any of the
upper 32 bits causes an exception, #GP(0).
In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register
(operand-size prefixes are ignored). All 64 bits of DR0-DR3 are writable by software.
However, MOV DRn instructions do not check that addresses written to DR0-DR3 are
in the limits of the implementation. Address matching is supported only on valid
addresses generated by the processor implementation.
ters (DR0-DR7). The MOV instruction allows setup data to be loaded to and stored
from these registers.
On processors that support Intel 64 architecture, debug registers DR0-DR7 are 64
bits. In 32-bit modes and compatibility mode, writes to a debug register fill the upper
32 bits with zeros. Reads return the lower 32 bits. In 64-bit mode, the upper 32 bits
of DR6-DR7 are reserved and must be written with zeros. Writing one to any of the
upper 32 bits causes an exception, #GP(0).
In 64-bit mode, MOV DRn instructions read or write all 64 bits of a debug register
(operand-size prefixes are ignored). All 64 bits of DR0-DR3 are writable by software.
However, MOV DRn instructions do not check that addresses written to DR0-DR3 are
in the limits of the implementation. Address matching is supported only on valid
addresses generated by the processor implementation.
2.7.4
Invalidating Caches and TLBs
The processor provides several instructions for use in explicitly invalidating its caches
and TLB entries. The INVD (invalidate cache with no writeback) instruction invali-
dates all data and instruction entries in the internal caches and sends a signal to the
external caches indicating that they should be also be invalidated.
The WBINVD (invalidate cache with writeback) instruction performs the same func-
tion as the INVD instruction, except that it writes back modified lines in its internal
caches to memory before it invalidates the caches. After invalidating the internal
caches, WBINVD signals external caches to write back modified data and invalidate
their contents.
The INVLPG (invalidate TLB entry) instruction invalidates (flushes) the TLB entry for
a specified page.
and TLB entries. The INVD (invalidate cache with no writeback) instruction invali-
dates all data and instruction entries in the internal caches and sends a signal to the
external caches indicating that they should be also be invalidated.
The WBINVD (invalidate cache with writeback) instruction performs the same func-
tion as the INVD instruction, except that it writes back modified lines in its internal
caches to memory before it invalidates the caches. After invalidating the internal
caches, WBINVD signals external caches to write back modified data and invalidate
their contents.
The INVLPG (invalidate TLB entry) instruction invalidates (flushes) the TLB entry for
a specified page.
2.7.5
Controlling the Processor
The HLT (halt processor) instruction stops the processor until an enabled interrupt
(such as NMI or SMI, which are normally enabled), a debug exception, the BINIT#
signal, the INIT# signal, or the RESET# signal is received. The processor generates a
special bus cycle to indicate that the halt mode has been entered.
Hardware may respond to this signal in a number of ways. An indicator light on the
front panel may be turned on. An NMI interrupt for recording diagnostic information
may be generated. Reset initialization may be invoked (note that the BINIT# pin was
(such as NMI or SMI, which are normally enabled), a debug exception, the BINIT#
signal, the INIT# signal, or the RESET# signal is received. The processor generates a
special bus cycle to indicate that the halt mode has been entered.
Hardware may respond to this signal in a number of ways. An indicator light on the
front panel may be turned on. An NMI interrupt for recording diagnostic information
may be generated. Reset initialization may be invoked (note that the BINIT# pin was