NEC 30500B User Manual

©

1997,1999

©

1997

MIPS Technologies Inc.

µ

Document No. U12031EJ3V0DS00 (3rd edition)
Date Published August 1999 N CP(K)
Printed in Japan

The 

µ

PD30500 (V

R

5000), 

µ

PD30500A

 (V

R

5000A), and 

µ

PD30500B

 (V

R

5000B) are a high-performance,

64-bit RISC  (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed

by MIPS

TM

 Technologies Inc.

The instructions of the V

R

5000, V

R

5000A, and V

R

5000B are compatible with those of the V

R

3000

TM

 series and

V

R

4000

TM

 series and higher, and completely compatible with those of the V

R

10000

TM

.  Therefore, present applications

can be used as they are.

Under development

•

Employs 64-bit MIPS-based RISC architecture

•

High-speed processing

•

2-way super scalar 5-stage pipeline

•

5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (

µ

PD30500)

6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (

µ

PD30500A)

8 SPECint95, 8 SPECfp95, 423 MIPS (

µ

PD30500B)

•

High-speed translation buffer mechanism (TLB) (48 entries)

•

Address space

Physical:  36 bits, Virtual:  40 bits

•

Floating-point unit (FPU)

•

Sum-of-products operation instruction supported

•

Primary cache memory (instruction/data: 32K bytes each)

•

Secondary cache controller

•

Maximum operating frequency Internal : 200MHz (

µ

PD30500), 250 MHz (

µ

PD30500A), 300 MHz (

µ

PD30500B)

External: 100 MHz

•

External/internal multiple selectable from two to eight

•

Instruction set compatible with V

R

3000 and V

R

4000 series and higher (conforms to MIPS I, II, III, and IV)

•

Supply voltage: 3.3 V 

±

5% (

µ

PD30500)

Core:  2.5 V 

±

5%, I/O:  3.3 V 

±

5% (

µ

PD30500A)

Core:  1.8 V 

±

0.1 V, I/O:  3.3 V 

±

5% (

µ

PD30500B)

µ