Intel Pentium Mobile T2130 LF80539GE0361M Data Sheet

Datasheet

57

DBSY#

Input/

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for 
driving data on the FSB to indicate that the data bus is in use. The 
data bus is released after DBSY# is deasserted. This signal must 
connect the appropriate pins on both FSB agents.

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction cannot 
be guaranteed in-order completion. Assertion of DEFER# is normally 
the responsibility of the addressed memory or Input/Output agent. 
This signal must connect the appropriate pins of both FSB agents.

DINV[3:0]#

Input/

Output

DINV[3:0]# (Data Bus Inversion) are source synchronous and 
indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals 
are activated when the data on the data bus is inverted. The bus 
agent will invert the data bus signals if more than half the bits, within 
the covered group, would change level in the next cycle.

DPRSTP#

Not used  DPRSTP# is not used by Pentium dual-core mobile processor.

DPSLP#

Input

DPSLP# when asserted on the platform causes the processor to 
transition from the Sleep State to the Deep Sleep state. In order to 
return to the Sleep State, DPSLP# must be deasserted. DPSLP# is 
driven by the ICH7-M chipset.

DPWR#

Input

DPWR# is a control signal from the Intel

 

945 Express Chipset used to 

reduce power on the processor data bus input buffers.

DRDY#

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data 
transfer, indicating valid data on the data bus. In a multi-common 
clock data transfer, DRDY# may be deasserted to insert idle clocks. 
This signal must connect the appropriate pins of both FSB agents.

DSTBN[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

DINV[3]#

D[63:48]#

DINV[2]#

D[47:32]#

DINV[1]#

D[31:16]#

DINV[0]#

D[15:0]#

D[15:0]#, DINV[0]# 

DSTBN[0]#

D[31:16]#, DINV[1]# 

DSTBN[1]#

D[47:32]#, DINV[2]# 

DSTBN[2]#

D[63:48]#, DINV[3]# 

DSTBN[3]#