Intel Pentium Mobile T2080 LF80539GE0301M Data Sheet

14

Datasheet

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch free 

transitions.

• Low transition latency and large number of transitions possible per second.

— Processor core (including L2 cache) is unavailable for up to 10 µs during the 

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode.

— When the on-die thermal sensor indicates that the die temperature is too high, 

the processor can automatically perform a transition to a lower frequency/

voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to 

acceptable levels, an up transition to the previous frequency/voltage point 

occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions 

enabling better system level thermal management. 

• Enhanced thermal management features.

— Digital thermal sensor and thermal interrupts with Out of Specification 

detection and interrupt generation.

— TM1 in addition to TM2 in case of non successful TM2 transition.
— Dual-core thermal management synchronization. 

Each core in the processor implements an independent MSR for controlling Enhanced 

Intel SpeedStep Technology, but both cores must operate at the same frequency and 

voltage. The processor has performance state coordination logic to resolve frequency 

and voltage requests from the two cores into a single frequency and voltage request for 

the package as a whole. If both cores request the same frequency and voltage then the 

processor will transition to the requested common frequency and voltage. If the two 

cores have different frequency and voltage requests then the processor will take the 

highest of the two frequencies and voltages as the resolved request and transition to 

that frequency and voltage.

The Intel Pentium Dual-Core processors incorporate FSB low power enhancements:

• Dynamic  FSB  Power  Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On Die Termination disabling
• Low  V

CCP

 (I/O termination voltage)

The processor incorporates the DPWR# signal that controls the data bus input buffers 

on the processor. The DPWR# signal disables the buffers when not used and activates 

them only when data bus activity occurs, resulting in significant power savings with no 

performance impact. BPRI# control also allows the processor address and control input 

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows 

a reciprocal power reduction in chipset address and control input buffers when the