Intel Core 2 Duo U7500 U7500 User Manual

Specification Update 

 37 

The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and 

MSR_LER_TO_LIP (1DEH) may contain incorrect values after any of the following: 

•  Either STPCLK#, NMI (NonMaskable Interrupt) or external interrupts 

•  CMP or TEST instructions with an uncacheable memory operand followed by a 

conditional jump 

•  STI/POP SS/MOV SS instructions followed by CMP or TEST instructions and then 

by a conditional jump 

Implication:  When the conditions for this erratum occur, the value of the LER MSRs may be 

incorrectly updated. 

Workaround: None identified 

For the steppings affected, see the Summary Tables of Changes. 

Some processors may unexpectedly assert a false THERMTRIP# after a warm reset 

under certain environmental and operating conditions. Intel has observed this on a 

limited number of parts when they are operating at a core-to-bus ratio different from 

the ratio used at power-on. The issue is due to a thermal sensor circuit timing 

marginality event that causes the sensor to initiate a thermal shutdown. Under these 

conditions, upon RESET# assertion, some processors may assert a false THERMTRIP# 

even though their temperature is below normal THERMTRIP# activation temperature. 

A warm reset is different from a cold/power-on reset in that PWRGOOD remains 

active throughout the assertion of RESET#. 

Implication:  This issue may be observed during warm reset cycle testing or during the process of 

repeatedly entering and exiting the S3/S4/S5 sleep states. When this issue occurs, the 

processor may proceed with a thermal shutdown signaled by the assertion of 

processor THERMTRIP# and the platform will remove power from the CPU or the 

entire platform.  

Workaround: A BIOS update can be implemented to address this erratum. Note: This workaround 

does not cover all system configurations where warm resets are initiated by Intel® 

AMT. 

For the steppings affected, see the Summary Tables of Changes. 

Under a rare set of timing conditions and address alignment of instructions in a short 

nested loop sequence, software that contains multiple conditional jump instructions 

and spans multiple 16-byte boundaries, may cause a machine check exception or a 

system hang. 

Implication:  Due to this erratum, a machine check exception or a system hang may occur.