Motorola DG128 User Manual
15
PORTS AND CONNECTORS
PRU PORT
The Port Replacement Unit (PRU) provides simulation of the HC12 bus and control ports A, B,
E, and K so expanded memory can be used for single-chip application development. PRU
operation is enabled with external memory by CONFIG Switch 1 ON. The PRU also provides
control of the external memories and peripherals on the CMD912x board. Care should be
taken not to violate PRU operation constraints or user code operation could be rendered
inoperable until a RESET is performed.
E, and K so expanded memory can be used for single-chip application development. PRU
operation is enabled with external memory by CONFIG Switch 1 ON. The PRU also provides
control of the external memories and peripherals on the CMD912x board. Care should be
taken not to violate PRU operation constraints or user code operation could be rendered
inoperable until a RESET is performed.
PRU Ports A, B, E, and K are simulated ports due to the different drive characteristics of the
PRU logic device. Following are the characteristic differences between the HC12 and PRU
ports:
PRU logic device. Following are the characteristic differences between the HC12 and PRU
ports:
1) The PRU will drive ports to TTL levels with 24ma of source current. Greater than the
HC12.
2) The PRU provides pull-up resistance of 47K ohms to +5V is applied to all PRU ports. The
HC12 allows this to be optioned on input ports.
3) The PRU will only drive outputs high to +4V. The PRU port pull-up resistors raise the
output level to +5V with minimal drive.
4) PRU port inputs will indicate logic high if not driven due to the pull-up resistors.
The PRU will provide HC12 internal resource memory mapping support with constraints. The
user should be cautious to stay within the bounds of the constraints for proper operation of the
board. PRU constraints:
user should be cautious to stay within the bounds of the constraints for proper operation of the
board. PRU constraints:
1) The HC12 R/W, LSTRB, and ECLK signals must be enabled for correct operation of the
PRU.
2) The HC12 MODE register must have the IVIS, EME, and EMK bits enabled for correct
PRU operation.
3) The IVIS bit in the HC12 MODE register must be enabled prior to any HC12 internal
resource map changes from default locations.
4) HC12 internal Ram block (INITRM register) cannot be moved above $4000 hex.
5) HC12 internal Register block (INITRG register) cannot be moved above $8000 hex and is
treated as a 2K byte memory space.
6) HC12 internal EEprom block (INITEE register) is treated as a 4K Byte memory space.