Intel CM8063501287403 User Manual

 

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Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families 

Datasheet Volume One of Two

asserted, all processor supplies (VCC, VTTA, VTTD, VSA, VCCPLL, VCCD) must be 

removed within the timeframe provided. The temperature at which THERMTRIP_N 
asserts is not user configurable and is not software visible.

The Integrated Memory Controller (IMC) has two, independent mechanisms that cause 

system memory throttling:

• Open Loop Thermal Throttling (OLTT) and Hybrid OLTT (OLTT_Hybrid)
• Closed Loop Thermal Throttling (CLTT) and Hybrid CLTT (CLTT_Hybrid)

Pure energy based estimation for systems with no BMC or Intel® Management Engine 

(Intel® ME). No memory temperature information is provided by the platform or 

DIMMs. The CPU is informed of the ambient temperature estimate by the BIOS or by a 
device via the PECI interface. DIMM temperature estimates and bandwidth control are 

monitored and managed by the PCU on a per rank basis.

Temperature information is provided by the platform (for example, BMC or Intel ME) 
through PECI and the PCU interpolates gaps with energy based estimations.

The processor periodically samples temperatures from the DIMM TSoD devices over a 

programmable interval. The PCU determines the hottest DIMM rank from TSoD data 
and informs the integrated memory controller for use in bandwidth throttling decisions.

The processor periodically samples temperature from the DIMM TSoD devices over a 
programmable interval and interpolates gaps or the BMC/Intel ME samples a 

motherboard thermal sensor in the memory subsection and provides this data to the 

PCU via the PECI interface. This data is combined with an energy based estimations 
calculated by the PCU. When needed, system memory is then throttled using CAS 

bandwidth control. The processor supports dynamic reprogramming of the memory 

thermal limits based on system thermal state by the BMC or Intel ME.

The processor includes a pair of new bi-directional memory thermal status signals 

useful for manageability schemes. Each signal presents and receives thermal status for 
a pair of memory channels (channels 0 & 1 and channels 2 & 3). 

• Input Function: The processor can periodically sense the MEM_HOT_{C01/C23}_N 

signals to detect if the platform is requesting a memory throttling event. 

Manageability hardware could drive this signal due to a memory voltage regulator 
thermal or electrical issue or because of a detected system thermal event (for 

example, fan is going to fail) other system devices are exceeding their thermal 

target. The input sense period of these signals are programmable, 100 us is the 
default value. The input sense assertion time recognized by the processor is 

programmable, 1 us is the default value. If the sense assertion time is programmed