Intel CM8063501287403 User Manual
Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families
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Datasheet Volume One of Two
Interfaces
The Intel® QuickPath Interconnect has an efficient architecture allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol
optimized for low latency and high scalability, as well as packet and lane structures
enabling quick completions of transactions. Reliability, availability, and serviceability
features (RAS) are built into the architecture.
interconnect performance to be achieved in real systems. It has a snoop protocol
optimized for low latency and high scalability, as well as packet and lane structures
enabling quick completions of transactions. Reliability, availability, and serviceability
features (RAS) are built into the architecture.
The physical connectivity of each interconnect link is made up of twenty differential
signal pairs plus a differential forwarded clock. Each port supports a link pair consisting
of two uni-directional links to complete the connection between two components. This
supports traffic in both directions simultaneously. To facilitate flexibility and longevity,
the interconnect is defined as having five layers: Physical, Link, Routing, Transport,
signal pairs plus a differential forwarded clock. Each port supports a link pair consisting
of two uni-directional links to complete the connection between two components. This
supports traffic in both directions simultaneously. To facilitate flexibility and longevity,
the interconnect is defined as having five layers: Physical, Link, Routing, Transport,
and Protocol.
• The Physical layer consists of the actual wires carrying the signals, as well as
circuitry and logic to support ancillary features required in the transmission and
receipt of the 1s and 0s. The unit of transfer at the Physical layer is 20-bits, which
is called a Phit (for Physical unit).
receipt of the 1s and 0s. The unit of transfer at the Physical layer is 20-bits, which
is called a Phit (for Physical unit).
• The Link layer is responsible for reliable transmission and flow control. The Link
layer’s unit of transfer is 80-bits, which is called a Flit (for Flow control unit).
• The Routing layer provides the framework for directing packets through
the fabric.
• The Transport layer is an architecturally defined layer (not implemented in
the initial products) providing advanced routing capability for reliable
end-to-end transmission.
• The Protocol layer is the high-level set of rules for exchanging packets of data
between devices. A packet is comprised of an integral number of Flits.
The Intel® QuickPath Interconnect includes a cache coherency protocol to keep the
distributed memory and caching structures coherent during system operation. It
supports both low-latency source snooping and a scalable home snoop behavior. The
coherency protocol provides for direct cache-to-cache transfers for optimal latency.
distributed memory and caching structures coherent during system operation. It
supports both low-latency source snooping and a scalable home snoop behavior. The
coherency protocol provides for direct cache-to-cache transfers for optimal latency.
2.5
Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the
bit value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate
established with every message. In this way, it is highly flexible even though underlying
logic is simple.
established with every message. In this way, it is highly flexible even though underlying
logic is simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 Kbps to 2 Mbps
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
accuracy requirements