Intel CM8063501287403 User Manual

Intel® Xeon® Processor E5-1600 v2/E5-2600 v2 Product Families

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Datasheet Volume One of Two

 

A System Management Interrupt (SMI) handler returns execution to either Normal 

state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software 
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide

 for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other 
threads. For more information on C1E, see 

To operate within specification, BIOS must enable the C1E feature for all installed 

processors. Please refer to the Intel® Xeon® Processor E5 v2 Product Family Processor 
Datasheet, Volume Two: Registers

 for more details.

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to 
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its 

L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while 

maintaining its architectural state. All core clocks are stopped at this point. Because the 
core’s caches are flushed, the processor does not wake any core that is in the C3 state 

when either a snoop is detected or when another core accesses cacheable memory. 

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an 

MWAIT(C6) instruction. Before entering core C6, the core will save its architectural 

state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero 
volts. In addition to flushing core caches core architecture state is saved to the uncore. 

Once the core state save is completed, core voltage is reduced to zero. During exit, the 

core is powered on and its architectural state is restored.

The Delayed Deep C-states (DDCst) feature on this processor replaces the “C-state 

auto-demotion” scheme used in the previous processor generation. Deep C-states are 
defined as CC3 through CC6 (refer to 

 for supported deep c-states).

The Delayed Deep C-states are intended to allow a staged entry into deeper C-states 
whereby the processor enters a lighter, short exit-latency C-state (core C1) for a period 

of time before committing to a long exit-latency deep C-state (core C3 and core C6). 

This is intended to allow the processor to get past the cluster of short-duration idles, 
providing each of those with a very fast wake-up time, but to still get the power benefit 

of the deep C-states on the longer idles. 

The processor supports C0, C1/C1E, C2, C3, and C6 power states. The following is a 
summary of the general rules for package C-state entry. These apply to all package 

C-states unless specified otherwise:

• A package C-state request is determined by the lowest numerical core C-state 

amongst all cores.

• A package C-state is automatically resolved by the processor depending on the 

core idle power states and the status of the platform components.

— Each core can be at a lower idle power state than the package if the platform 

does not grant the processor permission to enter a requested package C-state.