Intel BX80637I53350P User Manual

52

Specification Update

Problem:

If a logical processor has EPT (Extended Page Tables) enabled, is using 32-bit PAE 
paging, and accesses the virtual-APIC page then a complex sequence of internal 
processor micro-architectural events may cause an incorrect address translation or 
machine check on either logical processor.

Implication:

This erratum may result in unexpected faults, an uncorrectable TLB error logged in 
IA32_MCi_STATUS.MCACOD (bits [15:0]) with a value of 0000_0000_0001_xxxxb 
(where x stands for 0 or 1), a guest or hyper visor crash, or other unpredictable system 
behavior.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the Summary Tables of Changes.

Problem:

The Intel® VT-d (Intel® Virtualization Technology for Directed I/O) hardware unit 
supporting the Processor Graphics device (

Bus 0; Device 2; Function 0) 

may not report 

address translation faults detected on Display Engine memory accesses when the 
Context Cache is disabled or during time periods when Context Cache is being 
invalidated.

Implication:

Due to this 

e

rratum, Display Engine accesses that fault are correctly aborted but may not 

be reported in the FSTS_REG fault reporting register (GFXVTDBAR offset 034H).

Workaround:

None identified

Status:

For the steppings affected, see the Summary Tables of Changes.