Intel Core 2 Duo T5300 187098 User Manual

16

Datasheet

The processor responds to snoop or interrupt transactions on the FSB while in Stop-

Grant state by entering the Stop-Grant Snoop state. The processor will stay in this 

state until the snoop on the FSB has been serviced (whether by the processor or 

another agent on the FSB) or the interrupt has been latched. The processor returns to 

the Stop-Grant state once the snoop has been serviced or the interrupt has been 

latched.

The Sleep state is a low-power state in which the processor maintains its context, 

maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is 

entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# 

pin should only be asserted when the processor is in the Stop-Grant state. SLP# 

assertions while the processor is not in the Stop-Grant state is out of specification and 

may result in unapproved operation. 

In the Sleep state, the processor is incapable of responding to snoop transactions or 

latching interrupt signals. No transitions or assertions of signals (with the exception of 

SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep 

state. Snoop events that occur while in Sleep state or during a transition into or out of 

Sleep state will cause unpredictable behavior. Any transition on an input signal before 

the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as 

specified in the RESET# pin specification, then the processor will reset itself, ignoring 

the transition through the Stop-Grant state. If RESET# is driven active while the 

processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted 

immediately after RESET# is asserted to ensure the processor correctly executes the 

Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power 

state, the Deep Sleep state, by asserting the DPSLP# pin (See 

). While 

the processor is in the Sleep state, the SLP# pin must be deasserted if another 

asynchronous FSB event needs to occur. 

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep 

state. BCLK may be stopped during the Deep Sleep state for additional platform level 

power savings. BCLK stop/restart timings on appropriate chipset-based platforms are 

as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within two BCLKs 

of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels 

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK 

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to 

allow for PLL stabilization) must occur before the processor can be considered to be in 

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter 

the Stop-Grant state.

While in the Deep Sleep state, the processor is incapable of responding to snoop 

transactions or latching interrupt signals. No transitions of signals are allowed on the 

FSB while the processor is in the Deep Sleep state. When the processor is in the Deep 

Sleep state it will not respond to interrupts or snoop transactions.