Intel Core 2 Duo T5300 187098 User Manual

Datasheet

19

Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep 

state or C6 will expand the L2 cache to two ways and invalidate previously disabled 

cache ways. If the L2 cache reduction conditions stated above still exist when the last 

core returns to C4 and the package enters the Intel Enhanced Deeper Sleep state or 

C6, then the L2 will be shrunk to zero again. If a core requests a processor 

performance state resulting in a higher ratio than the predefined L2 shrink threshold, 

the C0 timer expires, or the second core (not the one currently entering the interrupt 

routine) requests the C1, C2, or C3 states, then the whole L2 will be expanded upon 

the next interrupt event.

In addition, the processor supports Full Shrink on L2 cache. When the MWAIT C6 

instruction is executed with a hint=0x2 in ECX[3:0], the micro code will shrink all the 

active ways of the L2 cache in one step. This ensures that the package enters C6 

immediately when both cores are in CC6 instead of iterating till the cache is reduced to 

zero. The operating system (OS) is expected to use this hint when it wants to enter the 

lowest power state and can tolerate the longer entry latency.

L2 cache shrink prevention may be enabled as needed on occasion through an 

MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not 

enter Intel Enhanced Deeper Sleep state or C6 since the L2 cache remains valid and in 

full size.

The processor features Enhanced Intel SpeedStep Technology. The key features of 

Enhanced Intel SpeedStep Technology follow:

• Multiple voltage and frequency operating points provide optimal performance at the 

lowest power. 

• Voltage and frequency selection is software controlled by writing to processor 

MSRs:

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps by placing new values on the VID pins, and the PLL then locks to the 

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency, and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch-free 

transitions.

• Low transition latency and large number of transitions possible per second:

— Processor core (including L2 cache) is unavailable for up to 10 μs during the 

frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.