Intel Intel Core2 Extreme QX6850 HH80562XJ0808M Data Sheet
Product codes
HH80562XJ0808M
Datasheet
23
Electrical Specifications
NOTES:
1.
1.
Refer to
for signal descriptions.
2.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See
processor configuration options. See
for details.
4.
PROCHOT# signal type is open drain output and CMOS input.
.
2.6.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/
deasserted for at least four BCLKs in order for the processor to recognize the proper
for the DC specifications. See
for additional
timing requirements for entering and leaving the low power states.
2.6.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads)
unless otherwise stated. All specifications apply to all frequencies and cache sizes
unless otherwise stated.
Table 8.
Signal Characteristics
Signals with R
TT
Signals with No R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#,
TESTHI[13,11:10,7:0], VID[7:0],
GTLREF[3:0], TCK, TDI, TMS, TRST#,
MSID[1:0], VTT_SEL
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#,
TESTHI[13,11:10,7:0], VID[7:0],
GTLREF[3:0], TCK, TDI, TMS, TRST#,
MSID[1:0], VTT_SEL
Open Drain Signals
1
NOTES:
1.
Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BPMb[3:0]#, BR0#, TDO, FCx
BPMb[3:0]#, BR0#, TDO, FCx
Table 9.
Signal Reference Voltages
GTLREF
V
TT
/2
BPM[5:0]#, BPMb[3:0]#, RESET#, BNR#, HIT#,
HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,
REQ[4:0]#, RS[2:0]#, TRDY#
HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#,
BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#,
REQ[4:0]#, RS[2:0]#, TRDY#
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD
IGNNE#, INIT#, PROCHOT#,
PWRGOOD
1
, SMI#, STPCLK#, TCK
, TRST#
NOTES:
1.
These signals also have hysteresis added to the reference voltage. See
for more
information.