Intel Intel Core2 Extreme QX6850 HH80562XJ0808M Data Sheet

Datasheet

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 Static and Transient Tolerance ............................................................................. 20

 Overshoot Example Waveform ............................................................................. 21

Differential Clock Crosspoint Specification ................................................................... 29

10 Processor Land Coordinates and Quadrants, Top View ................................................... 37
11 land-out Diagram (Top View – Left Side) ..................................................................... 40
12 land-out Diagram (Top View – Right Side) ................................................................... 41
13 Thermal Profile 130 W Processors............................................................................... 74
14 Case Temperature (TC) Measurement Location ............................................................ 75
15 Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 77
16 Conceptual Fan Control on PECI-Based Platforms ......................................................... 79
17 Processor Low Power State Machine ........................................................................... 82

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References .............................................................................................................. 11

Voltage Identification Definition ................................................................................. 15

Absolute Maximum and Minimum Ratings.................................................................... 17

 Static and Transient Tolerance ............................................................................. 19

Signal Characteristics ............................................................................................... 23

10 GTL+ Signal Group DC Specifications.......................................................................... 24
11 Open Drain and TAP Output Signal Group DC Specifications ........................................... 24
12 CMOS Signal Group DC Specifications ......................................................................... 25
13 GTL+ Bus Voltage Definitions .................................................................................... 26
14 Core Frequency to FSB Multiplier Configuration ............................................................ 27
15 BSEL[2:0] Frequency Table for BCLK[1:0] ................................................................... 27
16 Front Side Bus Differential BCLK Specifications............................................................. 28
17 PECI DC Electrical Limits ........................................................................................... 30
18 Processor Loading Specifications ................................................................................ 35
19 Package Handling Guidelines ..................................................................................... 35
20 Processor Materials .................................................................................................. 36
21 Alphabetical Land Assignments .................................................................................. 42
22 Numerical Land Assignment....................................................................................... 52
23 Signal Description .................................................................................................... 62
24 Processor Thermal Specifications................................................................................ 72
25 Thermal Profile 130 W Processors............................................................................... 73
26 GetTemp0() and GetTemp1() Error Codes ................................................................... 80
27 Power-On Configuration Option Signals ....................................................................... 81