Intel PCI User Manual
Software Developer’s Manual
201
PHY Functionality and Features
11.13.1
Link Test
In 10 Mbps mode, the PHY always transmits link pulses. If the Link Test Function is enabled, it
monitors the connection for link pulses. Once it detects 2 to 7 link pulses, data transmission is
enabled and remains enabled as long as the link pulses or data reception continues. If the link
pulses stop, the data transmission is disabled.
pulses stop, the data transmission is disabled.
If the Link Test function is disabled, the PHY might transmit packets regardless of detected link
pulses. Setting PHY register 16d, bit 14 can disable the Link Test function.
11.13.2
10Base-T Link Failure Criteria and Override
Link failure occurs if Link Test is enabled and link pulses stop being received. If this condition
occurs, the PHY returns to the Auto-Negotiation phase if Auto-Negotiation is enabled. Setting
PHY register 16d, bit 14 disables the Link Integrity Test function, then the PHY transmits packets,
regardless of link status.
regardless of link status.
11.13.3
Jabber
If the MAC begins a transmission that exceeds the jabber timer, the PHY disables the Transmit and
loopback functions and asserts collision indication to the MAC. The PHY automatically exits
loopback functions and asserts collision indication to the MAC. The PHY automatically exits
jabber mode after 250-750 ms. This function can be disabled by setting PHY register 16d, bit 10 to
1b.
11.13.4
Polarity Correction
The PHY automatically detects and corrects for the condition where the receive signal
(MDI_PLUS[0]/MDI_MINUS[0]) is inverted. Reversed polarity is detected if eight inverted link
pulses, or four inverted end-of-frame markers, are received consecutively. If link pulses or data are
pulses, or four inverted end-of-frame markers, are received consecutively. If link pulses or data are
not received for 96-130 ms, the polarity state is reset to a non-inverted state.
11.13.5
Dribble Bits
The PHY device handles dribble bits for all of its modes. If between one to four dribble bits are
received, the nibble is passed across the interface. The data passed across is padded with 1b’s if
necessary. If between five to seven dribble bits are received, the second nibble is not sent onto the
necessary. If between five to seven dribble bits are received, the second nibble is not sent onto the
internal MII bus to the MAC. This ensures that dribble bits between 1-7 do not cause the MAC to
discard the frame due to a CRC error.
11.14
PHY Line Length Indication
The PHY has a mechanism to deliver coefficient data for use in measuring cable length. If this
capability is required, please contact your Intel representative for details.
capability is required, please contact your Intel representative for details.